High-level Synthesis Method Research Articles

Design Automation of Neural Network Applications Using Formal Techniques—Rapid Prototyping Using the CCC Synthesizer

Cellular neural network (CNN) implementations used in real time image processing are rapidly generated by a formal High-level synthesis (HLS) toolset in this work. Industrial and academic hardware design projects can benefit from the use of the Custom Coprocessors Compilation (CCC) HLS behavioral synthesise, via the massive reduction in design and verification time. The CCC tool is built with formal compiler-compiler, Logic Programming and XML validation techniques, thus the generated RTL VHDL or Verilog models are provably-correct. In this work, we rapidly modeled CNNs in the ADA programming language, compiled and verified along with all the necessary testbenches in GNU ADA. Edge-detection, halftoning and morphological processing applications were prototyped, so as to evaluate the CCC HLS method, which was the main contribution of this work. The combination of Logic Programming and RDF validation techniques, as well as prototyping of CNN applications made this work unique.

Machine learning predictive modelling high-level synthesis design space exploration

A machine learning-based predictive model design space exploration (DSE) method for high-level synthesis (HLS) is presented. The method creates a predictive model for a training set until a given error threshold is reached and then continues with the exploration using the predictive model avoiding time-consuming synthesis and simulations of new configurations. Results show that the authors' method is on average 1.92 times faster than a genetic-algorithm DSE method generating comparable results, whereas it achieves better results when constraining the DSE runtime. When compared with a previously developed simulated annealer (SA)-based method, the proposed method is on average 2.09 faster, although again achieving comparable results.

High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability

A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay-fault coverage is usually attributed to the fact that a two-pattern test for delay testing cannot be delivered to modules under test in two consecutive cycles. To solve the problem, we propose an HLTS method that ensures that valid test pairs can be sent to each module through synthesized circuit hierarchy. Experimental results show that this method achieves 100% fault coverage for transition faults in modules; in contrast, the fault coverage in circuits synthesized by a left-edge-algorithm-based allocation algorithm is rather poor. The area overhead due to this method ranges from 1% to 10% for 16-b datapath circuits. On the other hand, hierarchical test patterns cannot provide good delay-fault coverage for faults in interconnection structure and registers. The reason is that some control sequences required for delay-fault detection cannot be provided by the controller. We propose two design-for-testability insertion methods to deal with this problem. Experimental results show that, on the average, at least 11% higher delay-fault coverage is achieved by these methods.

VERIFICATION OF DATAFLOW SCHEDULING

This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-model-verifier (SMV) techniques. Formal verification in high-level design means architecture verification, which is different from functional verification in register transfer level (RTL). Generally, dataflow algorithms need algorithmic transformations to achieve optimal goals and also need design scheduling to allocate processor resources before mapping on a silicon. However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. Instead of applying Boolean algebra in traditional verification, this paper adopts both Petri Net theory and SMV model checker to verify the correctness of the synthesis results of the high-level dataflow designs. In the proposed hybrid verification method, a high-level design or DUV (design-under-verification) is first transformed into a Petri Net model. Then, Petri Net theory is applied to check the correctness of its algorithmic transformations of HLS, and the SMV model checker is used to verify the correctness of the design scheduling. We presented two approaches to realize the proposed verification method and concluded the best one who outperforms the other in terms of processing speed and resource usage.

Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures

In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.

Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique

High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.

Application of symbolic computer algebra in high-level data-flow synthesis

The growing market of multimedia applications has required the development of complex application-specified integrated circuits with significant data-path portions. Unfortunately, most high-level synthesis tools and methods cannot automatically synthesize data paths such that complex arithmetic library blocks are intelligently used. Namely, most arithmetic-level optimizations are not supported and they are left to the designer's ingenuity. In this paper, we show how symbolic algebra can be used to construct arithmetic-level decomposition algorithms. We introduce our tool, SymSyn, that optimizes and maps data flow descriptions into data paths using complex arithmetic components. SymSyn uses two new algorithms to find either minimal component mapping or minimal critical path delay (CPD) mapping of the data flow. In this paper, we give an overview of the proposed algorithms. We also show how symbolic manipulations such as tree-height-reduction, factorization, expansion, and Horner transformation are incorporated in the preprocessing step. Such manipulations are used as guidelines in initial library element selection to accelerate the proposed algorithms. Furthermore, we demonstrate how substitution can be used for multiexpression component sharing and CPD optimization.

High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems Based on Logic-in-Memory Structure

One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain.A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.

A new approach to built-in self-testable datapath synthesis based on integer linear programming

The focus of high-level built-in self-test (BIST) synthesis is register assignment, which involves system register assignment, BIST register assignment, and interconnection assignment. To reduce the complexity involved in the assignment process, existing high-level BIST synthesis methods decouple the three tasks and perform the tasks sequentially at the cost of global optimality. They also try to achieve only one objective: minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we propose a new approach to the BIST data path synthesis based on integer linear programming that performs the three register assignment tasks concurrently to yield optimal designs. In addition, our approach finds an optimal register assignment for each k-test session. Therefore, it offers a range of designs with different figures of merit in area and test time. Our experimental results show that our method successfully synthesizes a BIST circuit for every k-test session for all six circuits experimented. All the BIST circuits are better in area overhead than those generated by existing high-level BIST synthesis methods.

High-level test synthesis: a survey

This paper surveys the various high-level design for testability and synthesis for testability methods that have been proposed in the last decade. We begin with a description of high-level synthesis methods which target the ease of subsequent gate-level sequential test generation. Then we describe high-level synthesis methods which target built-in self-test (BIST) and hierarchical testability. Thereafter, we describe register-transfer level testability techniques that target gate-level test generation, BIST and hierarchical testability. We then describe some high-level test generation methods in brief.

An approach to test synthesis from higher level

Consideration to testability from the early stage in the design process is one of the most effective ways to reduce testing cost. This paper addresses approaches to high-level test synthesis, especially for testability targeting non-scan design. We give a brief survey of such approaches and introduce our approach. We present a high-level test synthesis method that considers testability of generated register-transfer level (RTL) data paths, as well as their area and performance. This work is mainly different from the related works in the following two points. (1) Our target is weak testability which is a testability measure of RTL data paths whose target is non-scan design for sequential automatic test pattern generation. (2) We take testability into consideration from the beginning of high-level synthesis. We consider testability during both scheduling and binding, while most related works (except for a few) consider testability during binding after scheduling. We propose a heuristic synthesis algorithm that generates a weakly testable data path while minimizing area under a performance constraint.

Latency minimisation by system clock optimisation

Performance of a system clock design depends on the operating clock period and cycle count, which is the same as the number of control steps for a design without loops. A method is proposed which maximises performance by adjusting the clock period and cycle count. Experimental results show that this method reduces the latency by 29.4% on average, compared to the conventional high-level synthesis method.

VASS—A VLSI array system synthesizer

This paper presents a computer-aided design environment called VASS, which assists the VLSI array design. It applies a systematic methodology to synthesize a competitive array system from a behavioral description. Special features include the multiple projection and the two level pipeline techniques. Several crucial issues are considered and some practical solutions are incorporated into VASS. For example, an effective approach is used to transport all the interior I/O to the boundaries of the array. Besides, VASS can generate a kind of control signals, called tags, which propagate with data through the whole array to specify the appropriate functions of each processing element at the appropriate time step. Also, based on the inherent characteristics of the systolic algorithms, a high level synthesis method is proposed to facilitate the datapath generation of processing elements in the resultant array. The automatic specification of control signals and datapath generation of the processing elements render VASS a complete VLSI array system synthesizer. With VASS, one can quickly inspect various array implementations for an algorthm and iteratively improve them to meet the demands of an application-specific VLSI array system.

High-level synthesis of data paths for easy testability

The paper presents a method for high-level synthesis of easy testable data paths from a given behavioural description of a design. The synthesis process uses an approach based on a problem-space genetic algorithm (PSGA) to perform integrated scheduling, allocation of testable functional units and registers under area, delay and testability constraints. Testability at behavioural level can be enhanced by minimising the number of self-adjacent registers (self-loops). The main objective is to minimise the testability overhead (area and delay) while searching the design-space to provide a self-loop free architecture. Experiments on benchmarks show that self-loops can be eliminated with minimum additional hardware resources.

A high-level datapath synthesis method for pipelined structures

This paper presents a model and a method for the high-level datapath synthesis of pipelined ASIC architectures, starting with a behavioural description of the system consisting of theoretical operational units with arbitrary operation duration. The method calculates the minimal number of buffers to be inserted, optimally selects the number of types of additional operational units, and determines the minimal number of required copies. The aim of the procedure is to ensure a latency which can be given in advance, and could not be achieved without additional buffers and extra copies of the operational units. The method provides a solution to the resource allocation problem by establishing a compatibility relation between the concurrent operations. The constraints for the types of processors to be applied can vary, depending upon the hardware resources.