An approach to test synthesis from higher level

Abstract

Consideration to testability from the early stage in the design process is one of the most effective ways to reduce testing cost. This paper addresses approaches to high-level test synthesis, especially for testability targeting non-scan design. We give a brief survey of such approaches and introduce our approach. We present a high-level test synthesis method that considers testability of generated register-transfer level (RTL) data paths, as well as their area and performance. This work is mainly different from the related works in the following two points. (1) Our target is weak testability which is a testability measure of RTL data paths whose target is non-scan design for sequential automatic test pattern generation. (2) We take testability into consideration from the beginning of high-level synthesis. We consider testability during both scheduling and binding, while most related works (except for a few) consider testability during binding after scheduling. We propose a heuristic synthesis algorithm that generates a weakly testable data path while minimizing area under a performance constraint.