Abstract
In this paper a non-scan design method for testability using thru operation is proposed for register transfer level data paths. First, the weak testability of data paths is defined, and the problem of making data paths weakly testable with small overhead is considered. It is shown that this problem is NP-complete and a heuristic algorithm for solving it is presented. Next a measure for the number of clock pulses that are necessary to control and observe registers is proposed, and its relationship to the test generation time is discussed. Finally the effectiveness of the method and the proposed measures are demonstrated with the results of experiments.
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