The Effect of Latency Increasing on the Realisation Cost in High Level Synthesis of Pipeline Systems

Abstract

This paper examines the effects of increasing the latency in pipeline systems. The high level synthesis methods focus on the pipeline throughput only, and the latency is an output parameter. The proposed method is capable for reducing the cost of the implementation by increasing the latency at the same throughput. The essence of the proposed method is that an increase in the latency may increase the mobility ranges of the processing units. Thus, the increased degrees of freedom may cause better implementation by affecting the scheduling and allocation steps. An impact assessment algorithm for calculating proper latency increment range is also presented.