A heterogeneous hardware scheme for accelerating the image reconstruction process of electrical tomography

Abstract

Currently, most of the electrical tomography measurement systems are developed on microcontroller units, digital signal processors, or field programmable gate arrays, whereas image reconstruction and display functions are implemented in a separate host computer. Therefore, the complete hardware usually comprises a measurement system and an image reconstruction computer. The current trend is to develop industrial standard electrical tomography systems, which can implement the image reconstruction and measurement functions into an integrated processor/chip. However, most of the above mentioned processors do not provide the necessary computational resources as required by the computationally intensive image reconstruction function. This paper describes a hardware scheme for implementing image reconstruction functions on a heterogeneous hardware platform, wherein the processor system and programmable logics (PLs) are tightly coupled and can achieve better resource utilization and overall system performance. By adopting a high-level synthesis method, the image reconstruction algorithms can be realized jointly by the PLs and processor system. In this hardware scheme, the algorithms are properly optimized to achieve better data throughput and execution efficiency, that is, by utilizing parallel computation in PLs. Details of the hardware scheme and method of accelerating the image reconstruction process are presented in this paper. Implementation results show that the proposed heterogeneous hardware scheme can achieve the image reconstruction rates of 24 and 1700 frames per second while employing the iterative and non-iterative algorithms, respectively.