High-level Description Language Research Articles

Development of a Hardware-in-the-Loop Platform for the Validation of a Small-Scale Wind System Control Strategy

The use of renewable energies contributes to the goal of mitigating climate change by 2030. One of the fastest-growing renewable energy sources in recent years is wind power. Large wind generation systems have drawbacks that can be minimized using small wind systems and DC microgrids (DC-µGs). A wind system requires a control system to function correctly in different regions of its operating range. However, real-time analysis of a physical wind system may not be feasible. An alternative to counteract this disadvantage is using real-time hardware in the loop (HIL) simulation. This article describes the implementation of an HIL platform in an NI myRIO 1900 to evaluate the performance of control algorithms in a small wind system (SWS) that serves as a distributed generator for a DC-µG. In the case of an SWS, its implementation implies nonlinear behaviors and, therefore, nonlinear equations, and this paper shows a way to do it by distributing the computational work, using a high-level description language, and achieving good accuracy and latency with a student-oriented development kit. The platform reproduces, with an integration time of 10 µs, the response of the SWS composed of a 3.5 kW turbine with a fixed blade pitch angle and no gear transmission, a permanent magnet synchronous generator (PMSG), and a three-phase full-bridge AC/DC electronic power converter. The platform accuracy was validated by comparing its results against a software simulation. The compared variables were the PMSG currents in dq directions, the turbine’s angular speed, and the DC bus’s voltage. These comparisons showed mean absolute errors of 0.04 A, 1.9 A, 0.7 rad/s, and 9.5 V, respectively. The platform proved useful for validating the control algorithm, exhibiting the expected results in comparison with a lab-scale prototype using the same well-known control strategy. Using a well-known control strategy provides a solid reference to validate the platform.

Optimization on operation sorting for HLS scheduling algorithms

High-Level Synthesis (HLS) automates hardware design from high-level language descriptions, enhancing design efficiency and reducing cycles. Operation scheduling, a critical step in HLS, determines system latency. Due to the NP-hard nature of scheduling problem, existing algorithms adopt heuristic approaches, scheduling operations sequentially. In this paper, we present a rigorous proof establishing the direct correspondence between the balanced state and the optimal scheduling. Additionally, we demonstrate the existence of operation scheduling sequences that achieve optimal results. Building on these findings, we propose a resource-constrained list scheduling algorithm. We introduce a novel priority function for the classic list scheduling algorithm to determine the scheduling order. Furthermore, we extend our approach to enhance the latency-constrained entropy-directed scheduling algorithm by altering the scheduling order. Experimental results validate the effectiveness of our novel priority function in addressing both resource-constrained and latency-constrained scheduling problems. Our algorithm achieves a near-optimal scheduling solution while maintaining low time complexity.

Quantifying means-end reasoning skills in simulation-based training: a logic-based approach

We develop a logic-based approach for designing simulation-based training scenarios. Our methodology embodies a concise definition of the scenario concept and integrates the notions of training goals, acceptable versus unacceptable actions and performance scoring. The approach applies classical artificial intelligence (AI) planning to extract coherent plays from a causal description of the training domain. The domain- and task-specific parts are defined in a high-level action description language [Formula: see text]. Generic causal and temporal logic is added when the causal theory is compiled into the underlying Answer Set Programming (ASP) language. The ASP representation is used to derive a scoring function that reflects the quality of a play or training session, based on a distinction of states and actions into green (acceptable) and red (unacceptable) ones. To that end, we add to the casual theory a set of norms that specify an initial assignment of colors. The ASP engine uses these norms as axioms and propagates colors by consulting the causal theory. We prove that any set of such norms constitutes a conservative extension of the underlying causal theory. With this work, we hope to lay the foundation for the development of design and analysis tools for exercise managers. We envision a software system that lets an exercise manager view all plays of a tentative scenario design, with expediency information and scores for each possible play. Our approach is applicable to any domain in which means-ends reasoning is pertinent. We illustrate the approach in the domain of crisis response and management.

OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs

Demanded by ever-evolving data processing algorithms, field-programmable gate arrays (FPGAs) have become essential components of modern computing systems, thanks to their reconfigurable and distributed computing capabilities. However, FPGAs are among the very few integrated chips that still require long development cycles and high human efforts, even for industrial vendors. In this article, we introduce OpenFPGA, an open-source framework that can automate and significantly accelerate the development cycle of customizable FPGA architectures. OpenFPGA allows users to customize their FPGA architectures down to circuit-level details using a high-level architecture description language and autogenerate associated Verilog netlists which can be used in a backend flow to generate production-ready layouts. A generic Verilog-to-Bitstream generator is also provided, allowing end-users to implement practical applications on any FPGAs that OpenFPGA can support. Using OpenFPGA, we demonstrate less than 24-h layout generation of two FPGA fabrics, which are based on a Stratix-like architecture built with a commercial 12-nm standard cell library and 40-nm custom cells, respectively.

L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor

The L0TP+ initiative is aimed at the upgrade of the FPGA-based Level-0 Trigger Processor (L0TP) of the NA62 experiment at CERN for the post-LS2 data taking, which is expected to happen at 100% of design beam intensity, corresponding to about 3.3 × 1012 protons per pulse on the beryllium target used to produce the kaons beam. Although tests performed at the end of 2018 showed a substantial robustness of the L0TP system also at full beam intensity, there are several reasons to motivate such an upgrade: i) avoid FPGA platform obsolescence, ii) make room for improvements in the firmware design leveraging a more capable FPGA device, iii) add new functionalities, iv) support the 4 beam intensity increase foreseen in future experiment upgrades. We singled out the Xilinx Virtex UltraScale+ VCU118 development board as the ideal platform for the project. L0TP+ seamless integration into the current NA62 TDAQ system and exact matching of L0TP functionalities represent the main requirements and focus of the project; nevertheless, the final design will include additional features, such as a PCIe RDMA engine to enable processing on CPU and GPU accelerators, and the partial reconfiguration of trigger firmware starting from a high level language description (C/C++). The latter capability is enabled by modern High Level Synthesis (HLS) tools, but to what extent this methodology can be applied to perform complex tasks in the L0 trigger, with its stringent latency requirements and the limits imposed by single FPGA resources, is currently being investigated. As a test case for this scenario we considered the online reconstruction of the RICH detector rings on an HLS generated module, using a dedicated primitives data stream with PM hits IDs. Besides, the chosen platform supports the Virtex Ultrascale+ FPGA wide I/O capabilities, allowing for straightforward integration of primitive streams from additional sub-detectors in order to improve the performance of the trigger.

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can automatically generate Verilog and SPICE netlists based on realistic FPGA configurations and a high-level eTtensible Markup Language-based FPGA architectural description language. The outputted Verilog netlists can be used to generate layouts of full FPGA fabrics through a semicustom design flow. SPICE simulation decks can be generated at three levels of complexity, namely, full-chip-level, grid-level, and component-level, providing different tradeoff between accuracy and simulation time. In order to enable such level of analysis, we presented two SPICE netlist partitioning techniques: loads extraction and parasitic net activity estimation. Electrical simulations showed that averaged over the selected benchmarks, the grid-/component-level approach can achieve $6.1\times /7.5\times $ execution speed-up with 9.9%/8.3% accuracy loss, respectively, compared to the full-chip level simulation. FPGA-SPICE was showcased through three different case studies: 1) an area breakdown analysis for static random access memory-based FPGAs, showing that configuration memories are a dominant factor; 2) a power breakdown comparison to analytical models, analyzing the source of accuracy loss; and 3) a robustness evaluation against process corners, studying their impact on energy consumption of full FPGA fabrics.

Probabilistic timed graph transformation systems

Today, software has become an intrinsic part of complex distributed embedded real-time systems. The next generation of embedded real-time systems will interconnect the today unconnected systems via complex software parts and the service-oriented paradigm. Due to these interconnections, the architecture of systems can be subject to changes at run-time, e.g. when dynamic binding of service end-points is employed or complex collaborations are established dynamically. However, suitable formalisms and techniques that allow for modeling and analysis of timed and probabilistic behavior of such systems as well as of their structure dynamics do not exist so far.To fill the identified gap, we propose Probabilistic Timed Graph Transformation Systems (PTGTSs) as a high-level description language that supports all the necessary aspects of structure dynamics, timed behavior, and probabilistic behavior. We introduce the formal model of PTGTSs in this paper as well as present and formally verify a mapping of models with finite state spaces to probabilistic timed automata (PTA) that allows to use the PRISM model checker to analyze PTGTS models with respect to PTCTL properties.

Boosting Based Implementationof Biometric Authentication in IoT

In security and control application the biometric authentication played a specific and important role to identify the person. Analysis of face recognization is the prerequisite process for the entire authentication. This paper focuses an automatic real-time implementation of face recognization system by highlevel description language such as python. Comparing the biometrics where still images are used, video based biometric holds ample information than a single image. It provides the innovative solution for automatic real time face recognition from the video by the following algorithms like Adaboost, Haar cascade classifier and local binary pattern Histogram (LBPH). From the video stream, the input images are trained by adaboost algorithm which is implemented in cascade classifier. AdaBoost is called as adaptive boosting algorithm. It is a learning algorithm which has been combined with a weak classifier in order to form a strong classifier. Here, the real time testing image is compared with the 627 frames of trained images which are obtained from 47.7 MB (56088648 bytes) video. The hardware implementation of face recognization is obtained and the result can be stored and viewed in http://169.254.108.24. Thus by the above said procedures are authenticated by the combinational performance of Adaboost and Cascade classifier.

High-Level Asynchronous Concepts at the Interface Between Analog and Digital Worlds

Asynchronous circuits are becoming increasingly important in system design for Internet of Things, where they orchestrate the interface between big synchronous computation components and the analog environment, which is inherently asynchronous and has high uncertainty with respect to power supply, temperature, and long-term aging effects. However, wide adoption of asynchronous circuits by industrial users is hindered by a steep learning curve for asynchronous control models, such as signal transition graphs (STGs), that are developed by the academic community for specification, verification, and synthesis of asynchronous circuits. In this paper, we introduce a novel high-level description language for asynchronous circuits, which is based on behavioral concepts —high-level descriptions of asynchronous circuit requirements, that can be shared, reused, and extended by users, and can be automatically translated to STGs for further processing by conventional asynchronous and synchronous electronic design automation tools, such as Petrify and Mpsat. Our aim is to simplify the process of capturing system requirements in the form of a formal specification, and to promote behavioral concepts as a means for design reuse. The proposed design flow is fully automated in open-source toolsuite Workcraft, and is applied to the development of an asynchronous power regulator.

Enabling intent to configure scientific networks for high performance demands

Globally distributed scientific experiments involve movement of massive data volumes and many collaborators performing distributed data analysis. With complex workloads and heterogeneous resources, each user may desire certain behavior characteristics for their network paths. In this paper, we present the iNDIRA tool, which interacts with SDN north-bound interfaces to enable intent-based networking. It provides reliable, simple, and technology-agnostic communication between users and networks. Focusing particularly on science applications, iNDIRA uses natural language processing to construct semantic RDF graphs to understand, interact, and create the required network services. The technical challenges addressed by iNDIRA are: (1) development of a high-level descriptive language to query network-application requirements, (2) provides keyword identification and condition checking based on user profiles and topology details, (3) allows user negotiation based on the current network state, and (4) integrates network provisioning and service tools used by the application. iNDIRA is implemented on the ESnet network, where it interacts with OpenNSA (aka the NSI client) and Globus data transfer tools, to build complex cross-domain network paths for heterogeneous science applications, and perform secure data transfer. We argue that iNDIRA’s approach presents users with an alternative approach to interact and communicate their network demands, allowing seamless network service integration.

Modeling Hybrid Systems in SIMTHESys

Hybrid systems (HS) have been proven a valid formalism to study and analyze specific issues in a variety of fields. However, most of the analysis techniques for HS are based on low-level description, where single states of the systems have to be defined and enumerated by the modeler. Some high level modeling formalisms, such as Fluid Stochastic Petri Nets, have been introduced to overcome such difficulties, but simple procedures allowing the definitions of domain specific languages for HS could simplify the analysis of such systems. This paper presents a stochastic HS language consisting of a subset of piecewise deterministic Markov processes, and shows how SIMTHESys – a compositional, metamodeling based framework describing and extending formalisms – can be used to convert into this paradigm a wide number of high-level HS description languages. A simple example applying the technique to solve a model of the energy consumption of a data-center specified using Queuing Network and Hybrid Petri Nets is presented to show the effectiveness of the proposal.

A Comparison of Fluid Approximation and Stochastic Simulation for Evaluating Content Adaptation Systems

Performance evaluation plays an important role in system analysis. A compositional approach to model and evaluate content adaptation systems is presented in this paper, using the high-level system description and modelling language PEPA. Three computational methods, i.e. solving generator, stochastic simulation and fluid approximation, are demonstrated to derive performance measures from the PEPA model of content adaptation systems. A comprehensive comparison between these three computational methods shows that solving generator is only feasible for evaluating small scale systems, while for large scale systems the other two approaches are effective and promising. The simulation can achieve a high accuracy at high computational costs, while the fluid approximation approach can obtain an acceptable accuracy at a low cost. The consistence between the latter two computational methods is also studied.

Compositional Model Checking of Concurrent Systems

This paper presents a compositional framework to address the state explosion problem in model checking of concurrent systems. This framework takes as input a system model described as a network of communicating components in a high-level description language, finds the local state transition models for each individual component where local properties can be verified, and then iteratively reduces and composes the component state transition models to form a reduced global model for the entire system where global safety properties can be verified. The state space reductions used in this framework result in a reduced model that contains the exact same set of observably equivalent executions as in the original model, therefore, no false counter-examples result from the verification of the reduced model. This approach allows designs that cannot be handled monolithically or with partial-order reduction to be verified without difficulty. The experimental results show significant scale-up of this compositional verification framework on a number of non-trivial concurrent system models.

Enabling design and simulation of massive parallel nanoarchitectures

A common element in emerging nanotechnologies is the increasing complexity of the problems to face when attempting the design phase, because issues related to technology, specific application and architecture must be evaluated simultaneously. In several cases faced problems are known, but require a fresh re-think on the basis of different constraints not enforced by standard design tools.Among the emerging nanotechnologies, the two-dimensional structures based on nanowire arrays is promising in particular for massively parallel architectures. Several studies have been proposed on the exploration of the space of architectural solutions, but only a few derived high-level information from the results of an extended and reliable characterization of low-level structures.The tool we present is of aid in the design of circuits based on nanotechnologies, here discussed in the specific case of nanowire arrays, as best candidate for massively parallel architectures. It enables the designer to start from a standard High-level Description Languages (HDLs), inherits constraints at physical level and applies them when organizing the physical implementation of the circuit elements and of their connections. It provides a complete simulation environment with two levels of refinement. One for DC analysis using a fast engine based on a simple switch level model. The other for obtaining transient performance based on automatic extraction of circuit parasitics, on detailed device (nanowire-FET) information derived by experiments or by existing accurate models, and on spice-level modeling of the nanoarray. Results about the method used for the design and simulation of circuits based on nanowire-FET and nanoarray will be presented.

High-Level Synthesis for Accelerating the FPGA Implementation of Computationally Demanding Control Algorithms for Power Converters

Recent advances in power electronic converters highly rely on the development of new control algorithms. These implementations often require complex control architectures featuring microprocessors, digital signal processors, and field-programmable gate arrays (FPGAs). Whereas software implementations are feasible for most power electronics practitioners, FPGA implementations with ad-hoc digital hardware are often a challenging design task. This paper deals with the design and development of control systems for power converters using high-level synthesis tools. In particular, the Xilinx Vivado HLS tool is evaluated for the design of a computationally demanding application, the real-time load estimation for resonant power converters using parametric identification methods. The proposed methodology allows the designer to use a high-level description language, e.g., C, to describe the identification algorithm functionality, and the tool automatically generates the hardware floating-point data-path and the control unit. Besides, it allows a fast design-space exploration through synthesis directives, and pipelining and parallelization are automatically performed to meet timing constraints. The evaluation performed in the study-case control architecture shows a significant design complexity reduction. As a consequence, high-level synthesis tools should be considered as a new paradigm in accelerating digital design for power conversion systems.

Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems

Highly parallel systems are becoming mainstream in a wide range of sectors ranging from their traditional stronghold high-performance computing, to data centers and even embedded systems. However, despite the quantum leaps of improvements in cost and performance of individual components over the last decade (e.g., processor speeds, memory/interconnection bandwidth, etc.), system manufacturers are still struggling to deliver low-latency, highly scalable solutions. One of the main reasons is that the intercommunication latency grows significantly with the number of processor nodes. This article presents a novel way to reduce this intercommunication delay by implementing, in custom hardware, certain communication tasks. In particular, the proposed novel device implements the two most widely used procedures of the most popular communication protocol in parallel systems the Message Passing Interface (MPI). Our novel approach has initially been simulated within a pioneering parallel systems simulation framework and then synthesized directly from a high-level description language (i.e., SystemC) using a state-of-the-art synthesis tool. To the best of our knowledge, this is the first article presenting the complete hardware implementation of such a system. The proposed novel approach triggers a speedup from one to four orders of magnitude when compared with conventional software-based solutions and from one to three orders of magnitude when compared with a sophisticated software-based approach. Moreover, the performance of our system is from one to two orders of magnitude higher than the simulated performance of a similar but, relatively simpler hardware architecture; at the same time the power consumption of our device is about two orders of magnitude lower than that of a low-power CPU when executing the exact same intercommunication tasks.

NeuroFlow: FPGA-based Spiking Neural Network Acceleration with High-level Language Support

Event Abstract Back to Event NeuroFlow: FPGA-based Spiking Neural Network Acceleration with High-level Language Support Kit Cheung1*, Simon R. Schultz2 and Wayne Luk1 1 Imperial College London, Department of Computing, United Kingdom 2 Imperial College London, Department of Bioengineering, United Kingdom Spiking neural networks are a useful tool for cortical modelling and robotic control, but simulating a large network in real-time requires high-performance computers or specially built accelerators. Traditional accelerators for large-scale spiking neural network accelerators developed previously use Graphics Processing Units (GPUs) or Application-Specific Integrated Circuit (ASIC) chips. While ASICs deliver high performance, they lack the flexibility to reconfigure and hence are unable to adapt variation in the design and models employed. On the other hand, GPUs provides a decent speedup over multi-core CPUs and good flexibility, but it lacks scalability to handle larger networks. In this work we present NeuroFlow, a Field Programmable Gate Array (FPGA)-based spiking neural network accelerator consisting of 4 FPGAs. It supports the use of PyNN, a high-level simulator-independent network description language, to configure the hardware. A major novelty of the system is the capability to provide custom hardware configuration based on various simulation requirements, such as precision and time delay. The accelerator is implemented on an off-the-shelf MPC-C500 from Maxeler Technology which employs a streaming architecture in the FPGAs. The accelerator achieves the performance gain primarily by parallelizing the computation of point-neuron models and employing low-level optimization for synaptic data memory access. The accelerator currently supports basic PyNN functions such as spike-timing-dependent plasticity (STDP) and arbitrary postsynaptic current kernels. The system is able to support simulation of network of approximately 800,000 neurons, and achieve a real-time performance of 400,000 neurons for a network firing at 8Hz with random connections. With a single FPGA running at 150MHz, the accelerator delivers a throughput of 1.9 times to 3.5 times the performance of one of the most recent GPU-based accelerators in terms of postsynaptic potential delivery rate (Fidjeland et al., Neuroinformatics, 2012 Dec), subject to the simulated network and the GPU model used. In conclusion, while harnessing low-level customization and fine grained parallelism in FPGA, NeuroFlow is also able to provide the flexibility of a high-level platform such as GPUs and high-performance computers. It provides a promising alternative to accelerate spiking neural network simulations. Figure 1 Figure 2 Acknowledgements The research leading to these results has received funding from European Union Seventh Framework Programme under grant agreement number 287804, 248976 and 257906. The support by the Croucher Foundation, UK EPSRC, HiPEAC NoE, Maxeler University Program, and Xilinx is gratefully acknowledged. Keywords: FPGA, Spiking Neural network, PyNN, Hardware Acceleration, Dataflow Computing Conference: Neuroinformatics 2013, Stockholm, Sweden, 27 Aug - 29 Aug, 2013. Presentation Type: Oral presentation Topic: Neuromorphic engineering Citation: Cheung K, Schultz SR and Luk W (2013). NeuroFlow: FPGA-based Spiking Neural Network Acceleration with High-level Language Support. Front. Neuroinform. Conference Abstract: Neuroinformatics 2013. doi: 10.3389/conf.fninf.2013.09.00095 Copyright: The abstracts in this collection have not been subject to any Frontiers peer review or checks, and are not endorsed by Frontiers. They are made available through the Frontiers publishing platform as a service to conference organizers and presenters. The copyright in the individual abstracts is owned by the author of each abstract or his/her employer unless otherwise stated. Each abstract, as well as the collection of abstracts, are published under a Creative Commons CC-BY 4.0 (attribution) licence (https://creativecommons.org/licenses/by/4.0/) and may thus be reproduced, translated, adapted and be the subject of derivative works provided the authors and Frontiers are attributed. For Frontiers’ terms and conditions please see https://www.frontiersin.org/legal/terms-and-conditions. Received: 08 Apr 2013; Published Online: 11 Jul 2013. * Correspondence: Mr. Kit Cheung, Imperial College London, Department of Computing, London, United Kingdom, k.cheung11@imperial.ac.uk Login Required This action requires you to be registered with Frontiers and logged in. To register or login click here. Abstract Info Abstract Supplemental Data The Authors in Frontiers Kit Cheung Simon R Schultz Wayne Luk Google Kit Cheung Simon R Schultz Wayne Luk Google Scholar Kit Cheung Simon R Schultz Wayne Luk PubMed Kit Cheung Simon R Schultz Wayne Luk Related Article in Frontiers Google Scholar PubMed Abstract Close Back to top Javascript is disabled. Please enable Javascript in your browser settings in order to see all the content on this page.

Numerical Study of a 3D Two-Phase PEM Fuel Cell Model Via a Novel Automated Finite Element/Finite Volume Program Generator

AbstractNumerical methods of a 3D multiphysics, two-phase transport model of proton exchange membrane fuel cell (PEMFC) is studied in this paper. Due to the coexistence of multiphase regions, the standard finite element/finite volume method may fail to obtain a convergent nonlinear iteration for a two-phase transport model of PEMFC [49,50]. By introducing Kirchhoff transformation technique and a combined finite element-upwind finite volume approach, we efficiently achieve a fast convergence and reasonable solutions for this multiphase, multiphysics PEMFC model. Numerical implementation is done by using a novel automated finite element/finite volume program generator (FEPG). By virtue of a high-level algorithm description language (script), component programming and human intelligence technologies, FEPG can quickly generate finite element/finite volume source code for PEMFC simulation. Thus, one can focus on the efficient algorithm research without being distracted by the tedious computer programming on finite element/finite volume methods. Numerical success confirms that FEPG is an efficient tool for both algorithm research and software development of a 3D, multiphysics PEMFC model with multicomponent and multiphase mechanism.

Design, Analysis and Simulation of High Performance Low Power 8-Bit ALU at Gate and Layout Levels

In this work, the demand is to design an 8-bit ALU and perform analysis at gate and layout levels. The design makes use of n-Bit slice concept, the requirement is to design and develop low power high performance circuits. To achieve this, the design requires advanced styles to be employed. High level description language to be used to construct layout of 8-bit ALU and then different analyses will be carried out on this layout. Keywords - ALU, Bit Slice, Low Leakage, Threshold Volatge. I. INTRODUCTION An Arithmetic and Logic Unit (ALU) is a digital circuit that performs arithmetic and logic operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs, a single component may contain a number of ALUs. The ALU at one machine cycle executes a number of operations. During the process of operations it consumes a lot of power. Due to the power consumed by the ALU has a direct impact in the power dissipated from the processor. Hence, a design is required to implement the ALU in a fashion where the performance of the processor is improved and also the power consumed is less. This paper provides a simple design of a 8 Bit ALU for a speedy performance. This paper introduces a technique to design a ALU which consumes less power. Bit slice design is used for the construction of the 8-Bit ALU.

A Semantic Scene Description Language for Procedural Layout Solving Problems

Procedural content generation is becoming more and more relevant to solve the problem of content creation for the ever growing virtual worlds of games, simulations and other applications. However, these procedures are often unintuitive or use vague parameters, making it somewhat difficult for a designer to express his or her creative intent. Even worse, most of these techniques lack an accessible and easy to use interface.We have developed a generic layout solving approach to automatically create sensible content for virtual worlds. In that context, this paper proposes a high-level scene description language that allows designers to specify particular types of scenes. This description language allows designers to easily specify which objects need to be present in a scene, their attributes, and possible interrelationships. Application of the language, based on the rich vocabulary taken from a semantic library, is illustrated with several examples, showing its flexibility, intuitiveness and ease of use.