High-level Description Language Research Articles

High-performance computing using a reconfigurable accelerator

AbstractThis paper introduces the MoM-3 as a reconfigurable accelerator for high perform-ance computing at a moderate price. By using a new machine paradigm to trigger theoperations in the MoM-3, this accelerator is especially suited to scientific algorithms,where the hardware structure can be configured to match the structure of the algorithm.The MoM-3 efficiently uses reconfigurable logic devices to provide a fine-grain parallel-ism, and multiple address generators to have the complete memory bandwidth free fordata transfers (instead of fetching address computing instructions).Speed-up factors up to 82, compared to state-of-the-art workstations, are demon-strated by means of an Ising spin system simulation example. Adding the MoM-3 as anaccelerator allows to achieve supercomputer performance from a low-cost workstation. 1. Introduction Scientific computing provides the greatest challenges to modern workstations and even supercom-puters. A lot of different computer architectures have been presented, which take into account char-acteristics, that are common to many scientific algorithms. Vector processors [4] speed upoperations on large arrays of data by the use of pipelining techniques. Parallel multiprocessor archi-tectures [15] benefit from the fact, that many operations on large amounts of data are independentfrom each other. This allows to distribute these operations onto different processors (or processingelements) and execute them in parallel. But all of these architectures basically still follow thevon Neumann machine paradigm with a fixed instruction set, where the sequence of instructionstriggers the accesses to data in memory and the data manipulations.The Map-oriented Machine 3 (MoM-3) is an architecture based on the Xputer machine paradigm[3]. Instead of a hardwired ALU with a fixed instruction set, an Xputer has a reconfigurable ALUbased on field-programmable devices. All data manipulations, which are performed in the loopbodies of an algorithm, are combined to a set of compound operators. Each compound operatormatches a single loop body and takes several data words as input to produce a number of resultingdata words. The compound operators are configured into the field-programmable devices. Afterconfiguration, an Xputer’s “instruction set” consists only of the compound operators as they arerequired by the algorithm actually running on the Xputer. The combination of several operations ofa high level language description to one compound operator allows to introduce pipelining and finegrain parallelism to a larger extend, as can be done in fixed instruction set processors. E.g. interme-diate results can be passed along in the pipeline, instead of writing them back to the register fileafter every instruction. Since many scientific algorithms compute array indices in several nestedloops, the sequence of data addresses in a program trace shows a regular pattern. This leads to theidea to have complex address generators compute such address sequences from a small parameterset, which describes the address pattern. And instead of an instruction sequencer as a centralizedcontrol to trigger the operations in the reconfigurable ALU, the address generators themselves serveas a decentralized control. They automatically activate the appropriate compound operator, eachtime a new set of input data is fetched from memory and the previous results have been writtenback. This so-called data sequencing mechanism directly matches the loop structure of the algo-

CoLan: A functional constraint language and its implementation

This paper is about the definition of CoLan, a high-level declarative Constraint Description Language, for use with an Object-Oriented Database (OODB). CoLan has features of both first-order logic and functional programming and is based on Daplex. CoLan expressions are translated into Prolog code that implements the operational semantics of the constraint. Pieces of generated code are cached inside the class descriptor of the ‘host’ class attached to appropriate slots. The pieces of code are retrieved along an inheritance path when an update on the database is attempted. If the update violates any of the retrieved constraints then it is rejected with an informative message. Thus constraints are expressed declaratively and they can even be retracted individually. However, they are implemented efficiently as code-generated methods, triggered selectively by an update. The implementation is described for the ADAM OODB, which uses meta-classes of the CoLan system to generate class descriptions.

A knowledge-intensive genetic algorithm for supervised learning

Supervised learning in attribute-based spaces is one of the most popular machine learning problems studied and, consequently, has attracted considerable attention of the genetic algorithm community. The full-memory approach developed here uses the same high-level descriptive language that is used in rule-based systems. This allows for an easy utilization of inference rules of the well-known inductive learning methodology, which replace the traditional domain-independent operators and make the search task-specific. Moreover, a closer relationship between the underlying task and the processing mechanisms provides a setting for an application of more powerful task-specific heuristics. Initial results obtained with a prototype implementation for the simplest case of single concepts indicate that genetic algorithms can be effectively used to process high-level concepts and incorporate task-specific knowledge. The method of abstracting the genetic algorithm to the problem level, described here for the supervised inductive learning, can be also extended to other domains and tasks, since it provides a framework for combining recently popular genetic algorithm methods with traditional problem-solving methodologies. Moreover, in this particular case, it provides a very powerful tool enabling study of the widely accepted but not so well understood inductive learning methodology.

From a high level description of an IC to silicium: Don't loose design intent

During the development of the PRI ASIC we have faced with various design aspects of great interest: use of a High level Description Language, design exchange and technology upgrade, logic synthesis and loss of design intent. This circuit was first high level designed in C language, but at the synthesis time it was moved from one foundry to another changing CAD propietary's tools at the same time.

Wafer Scale Integration: A university perspective

This paper presents the Wafer Scale Integration research underway at our university. Specifically, we focus here on theApplications, Architectures, Design, and Test areas. Discussed are the philosophy of such an--admittedly aggressive--effort, the evolving infrastructure for the project, the application-driven architectures developed, and the design and test methodology. The first WSI design is a fully parallel FFT wafer, with application to a high-performance, high-speed CW jamming canceller. Other wafer level designs include an L-U decomposition array, using a newly-developed reciprocal cell, and a multipurpose PE array. The transition from basic tools, such as MAGIC, to commercial tools such as CADENCE, and the importance of a high level description language, VHDL, for modeling and simulation is emphasized. The discipline of reconfiguration, and the associated yield models, incorporating a harvesting factor, are also an integral part of the on-going project. Although, the first wafer will be reconfigured usingLaser linking and Cutting on the in-house laser table, alternative recon-figuration approaches for the other wafer designs are also being considered.

Generating Synthetic Workloads for Real-Time Systems

In this paper, we describe a software system which generates synthetic workloads for use in the performance evaluation of distributed real-time computer systems. The software system consists of a high-level description language and its compiler. The language provides a flexible, easy-to-use description of the structure and behavior of the real-time workload. The compiler, called a synthetic workload generator (SWG), uses this description to produce an executable synthetic workload (SW). The SW may then be used to drive the system under evaluation while measurements are being made.

Netlist compiler for ASIC design on a personal computer

This article presents the design and implementation of a personal computer (PC)-based netlist compiler for application-specific integrated circuit (ASIC) design. The netlist compiler system is an ASIC front-end design software tool, developed using the Turbo C programming language. This software tool enhances the design automation for ASIC design in the Philips Personal Design Station (PPDS) environment. It converts a high-level language description file written in a subset of VHDL (Very High Speed Integrated Circuit Hardware Description Language) into its gate-level implementation, using the Philips SystemCell II and SystemGate II library components.

A data flow technique for the efficient design of a class of parallel non-data flow signal processors

A system called net optimization and resource allocation (NORA) is introduced for the evaluation and programming of parallel signal processors, based on a data flow representation of the signal processing application. The main feature of this approach is that the scheduling and resource allocation can be done at compile time. It is made possible by the fact that most signal processing algorithms have constant data flow. The resulting hardware is much simpler because no overhead is needed for the real-time scheduling, as in usual data flow systems. Therefore a realization can easily be obtained using either commercially available components or VLSI technology. The proposed system comprises four main components: (1) a vector oriented data flow compiler for the translation of a high-level language description of algorithms into a data flow graph; (2) a critical path analysis for the evaluation of the minimal computation time of the algorithm, where block scheduling is assumed; (3) a schedule optimization for the determination of the minimal computation time under limited resources, not taking into account limitations imposed by the interconnection structure and temporary storage; and (4) a combined schedule optimization and resource allocation that maps a signal processing application onto a given hardware configuration and generates a formal microprogram.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simulation of a macro-pipelined multi-CPU event processor for use in FASTBUS

It is demonstrated how commercially available hardware description languages, which are normally used for hardware design verification at low to medium levels of modeling abstraction, can be used to optimize the design of complex real-time systems exhibiting concurrency. A high-performance, loosely coupled multiprocessor FASTBUS master intended for real-time event-processing applications is modeled. The performance of such a system depends on a large number of parameters that interact in a complex way, so that it becomes very difficult to make reliable tradeoffs in the design of the system architecture using an analytical approach. Given a high-level behavioral hardware description language and its simulator, it is shown that it is relatively easy to develop an executable model that provides a test bench for optimization of the architecture. >

A knowledge‐based software environment (KBSE) for designing concurrent processes

In this paper, we describe a knowledge‐based software environment (KBSE) which supports concurrent programming based on the framework of object‐oriented knowledge base. The object‐oriented knowledge base framework combines an object‐oriented data model with the logic programming paradigm. In KBSE, the user can describe a concurrent process with a set of (sequential) flowcharts and a set of coordination constraints and integrity constraints specified in a high level description language. The description is then synthesized into a Petri net representation. With the Petri net representation, existing analysis tools for Petri net can be fully utilized to assist the design and analysis of concurrent processes.

環境モデルを用いたロボット作業のオフラインプログラミングシステムの試作

A model-based off-line programming system of the robot operations is developed for industrial use. Environment modelling system based on the solid modelling system GEOMAP-III, is developed as a tool for maintaining the information of the working environment of the robot, such as robot itself, parts to be assembled, obstacles, etc., and other necessary information for the robotic tasks. A high-level assembly description language which describes assembly process in terms of the operations on the parts to be assembled instead of motion of the robot itself, is designed. By utilizing the information of the environment model, the system generates information of the robot motion from this high-level description, simulating the changes in the environment. Feasibility checks of the generated robot motion, detection of collisions between the robot and obstacles, calculation of necessary grasping force, are performed in the process and the results are displayed to the operator for easy debugging of the program. Preparation for sensory interactive robot motion in the run-time system, is also considered. As examples, some assembly operations are programmed by the system with high-level language.

A silicon compiler for digital signal processing: Methodology, implementation, and applications

This paper describes a fully integrated silicon compilation tool geared towards digital signal processing applications. The silicon compiler presented here uses a bit-serial architecture with a 1.25- µm CMOS cell library. It accepts as its input a high-level description language tailored for digital signal processing algorithms. The language supports the basic signal processing constructs such as multiplication, addition, subtraction, sample delays, logical operators, relational operators, as well as a conditional assignment. The compiler is equipped with behavioral, logic, and fault simulators, and performs placement and routing. The paper also details the use of the silicon compiler for the implementation of classical DSP algorithms: digital filters, FFT, programmable filters, as well as other more specialized applications such as adaptive algorithms and waveform synthesis. Moreover, some techniques are presented to implement more complex mathematical functions commonly used in DSP. The results of chip designs using the compiler and its impact on future designs are highlighted.

Performance time models for robot point operations

Point operations involve work performed under PTP control. Models to estimate performance time of such operations are proposed in the context of RTM. RTM, Robot Time and Motion, is a high-level robot task description language, which has been formulated to evaluate robot ability to perform a given task, estimate task execution time, and compare alternate robot work methods. In this article, the current capabilities of RTM are reviewed, and a simplified version for point operations is developed and demonstrated with Unimate 4000B in spot welding.

P-notation: High level description language for software design

The previous three parts of this series have outlined a notation for designing assembly language programs. In this final article the use of the notation is illustrated by designing a fairly large program by the process of stepwise refinement. Emphasis is placed on developing a modular structure by using the procedure and module constructs in order to simplify the design process and to facilitate testing.

P-notation: High level description language for software design

Top-down design of assembly language programs by the process of stepwise refinement is discussed and describes how modularization can be improved by the use of procedures and modules. The definition of procedures and modules in P-notation is presented and their implementation in assembly language given.

P-notation: High level description language for software design

A design approach is introduced in which assembly language programs are generated by direct translation of a high level description language called P-notation. P-notation encourages well structured program design and is tailored to translate simply and efficiently into assembly language by hand. After translation, the P-notation program description is retained as comments in the source listing, aiding documentation and maintenance.

The automatic synthesis of recursive programs

We describe a deductive technique for the automatic construction of recursive programs to meet given input-output specifications. These specifications express what conditions the output of the desired program is expected to satisfy. The deductive technique involves transforming the specifications by a collection of rules, summoned by pattern-directed function invocation. Some of these transformation rules express the semantics of the subject domain; others represent more general programming techniques. The rules that introduce conditional expressions and recursive calls into the program are discussed in some detail. The deductive techniques described are embedded in a running system called SYNSYS. This system accepts specifications expressed in high-level descriptive language and attempts to transform them into a corresponding LISP program. The transformation rules are expressed in the QLISP programming language. The synthesis of two programs performed by the system are presented. This research was supported in part by the Advanced Research Projects Agency of the Department of Defense under Contract MDA903-76-C-0206, by the National Science Foundation under Grant DCR72-03737 A01, by the Office of Naval Research under Contracts N00014-76-C-0687 and N00014-75-C-0816; and by a grant from the United States-Israel Binational Science Foundation (BSF), Jerusalem, Israel. The views and conclusions contained in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of Stanford University, Stanford Research Institute, or the U.S. Government.

The automatic synthesis of recursive programs

We describe a deductive technique for the automatic construction of recursive programs to meet given input-output specifications. These specifications express what conditions the output of the desired program is expected to satisfy. The deductive technique involves transforming the specifications by a collection of rules, summoned by pattern-directed function invocation. Some of these transformation rules express the semantics of the subject domain; others represent more general programming techniques. The rules that introduce conditional expressions and recursive calls into the program are discussed in some detail. The deductive techniques described are embedded in a running system called SYNSYS. This system accepts specifications expressed in high-level descriptive language and attempts to transform them into a corresponding LISP program. The transformation rules are expressed in the QLISP programming language. The synthesis of two programs performed by the system are presented. This research was supported in part by the Advanced Research Projects Agency of the Department of Defense under Contract MDA903-76-C-0206, by the National Science Foundation under Grant DCR72-03737 A01, by the Office of Naval Research under Contracts N00014-76-C-0687 and N00014-75-C-0816; and by a grant from the United States-Israel Binational Science Foundation (BSF), Jerusalem, Israel. The views and conclusions contained in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of Stanford University, Stanford Research Institute, or the U.S. Government.

Hardware Description Language Applications: An Introdiction and Prognosis

Just as Software designers use high-level languages like Algol, Fortran, PL/I, and Snobol to express algorithms in terms of language statements, so digital hardware designers use hardware description languages to describe the digital systems they want to design. But whereas compilers for many high-level programming languages have been developed and implemented, the process of transforming a high-level computer hardware description language specification of a system into a logic diagram is still in its infancy.