Abstract
The L0TP+ initiative is aimed at the upgrade of the FPGA-based Level-0 Trigger Processor (L0TP) of the NA62 experiment at CERN for the post-LS2 data taking, which is expected to happen at 100% of design beam intensity, corresponding to about 3.3 × 1012 protons per pulse on the beryllium target used to produce the kaons beam. Although tests performed at the end of 2018 showed a substantial robustness of the L0TP system also at full beam intensity, there are several reasons to motivate such an upgrade: i) avoid FPGA platform obsolescence, ii) make room for improvements in the firmware design leveraging a more capable FPGA device, iii) add new functionalities, iv) support the 4 beam intensity increase foreseen in future experiment upgrades. We singled out the Xilinx Virtex UltraScale+ VCU118 development board as the ideal platform for the project. L0TP+ seamless integration into the current NA62 TDAQ system and exact matching of L0TP functionalities represent the main requirements and focus of the project; nevertheless, the final design will include additional features, such as a PCIe RDMA engine to enable processing on CPU and GPU accelerators, and the partial reconfiguration of trigger firmware starting from a high level language description (C/C++). The latter capability is enabled by modern High Level Synthesis (HLS) tools, but to what extent this methodology can be applied to perform complex tasks in the L0 trigger, with its stringent latency requirements and the limits imposed by single FPGA resources, is currently being investigated. As a test case for this scenario we considered the online reconstruction of the RICH detector rings on an HLS generated module, using a dedicated primitives data stream with PM hits IDs. Besides, the chosen platform supports the Virtex Ultrascale+ FPGA wide I/O capabilities, allowing for straightforward integration of primitive streams from additional sub-detectors in order to improve the performance of the trigger.
Highlights
The NA62 experiment [1] is located at the CERN Super Proton Synchrotron (SPS) accelerator
A factor 10 in data reduction is obtained with the first level (L0) [5] based on a hardware processing pipeline – the L0 Trigger Processor (L0TP) [6] – implemented using an FPGA programmable logic device
Trigger primitives are produced in the same boards used for data readout [7] by some subdetectors (CHODs, MUV3, RICH, liquid krypton electromagnetic calorimeter (LKr), LAV) and sent to L0TP via Gigabit Ethernet (1GbE) links, using the UDP data transport protocol
Summary
A high intensity kaon beam is required to collect the statistics needed to reach an accuracy comparable to the theoretical one. Secondary particles of 75 GeV/c momentum are selected in a non separated beam composed of 6% of kaons, with a total rate of 750 MHz. Only about 10% of the kaons decay in flight along 65 m of decay volume, allowing the detector to collect ∼ 4.5 × 1012 decays per year. A Cerenkov counter (KTAG) identifies the K+ and three stations of Si pixel detectors (GTK) trace the beam particles. Annular lead-glass calorimeters (LAV) surround the decay volume for high angle photon detection. Hadron calorimeters (MUV1,2) and a plastic scintillator detector (MUV3) are used to identify muons. Data collected in 2016 and 2017, running between 40 and 70% of the maximum beam intensity, have been analyzed, achieving the best up–to–date single event sensitivity to the K+ → π+ννdecay. Analysis of data collected in 2018 is ongoing, as well as the preparation for the new data taking foreseen starting from 2021, when the experiment will run at full intensity
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