High-lead Solder Research Articles

Prognostication Based on Resistance-Spectroscopy and Phase-Sensitive Detection for Electronics Subjected to Shock-Impact

Leading indicators of failure have been developed based on high-frequency characteristics, and system-transfer function derived from resistance spectroscopy measurements during shock and vibration. The technique is intended for condition-monitoring in high-reliability applications where the knowledge of impending failure is critical and the risks in terms of loss-of-functionality are too high to bear. Previously, resistance spectroscopy measurements have been used during thermal cycling tests to monitor damage progression due to thermomechanical stresses. The development of resistance spectroscopy based damage precursors for prognostication under shock and vibration is new. In this paper, the high-frequency characteristics and system-transfer function based on resistance spectroscopy measurements have been correlated to the damage progression in electronics during shock and vibration. Packages being examined include ceramic area-array packages. Second level interconnect technologies examined include copper-reinforced solder column, SAC305 solder ball, and 90Pb10Sn high-lead solder ball. Assemblies have been subjected to 1500 g, 0.5 ms pulse (JESD-B2111). Continuity has been monitored in situ during the shock test for identification of part-failure. Resistance spectroscopy based damage precursors have been correlated to the optically measured transient strain based feature vectors. High speed cameras have been used to capture the transient strain histories during shock-impact. Statistical pattern recognition techniques have been used to identify damage initiation and progression and determine the statistical significance in variance between healthy and damaged assemblies. Models for healthy and damaged packages have been developed based on package characteristics. Data presented show that high-frequency characteristics and system-transfer characteristics based on resistance spectroscopy measurements can be used for condition-monitoring, damage initiation, and progression in electronic systems. A positive prognostic distance has been demonstrated for each of the interconnect technologies tested.

A novel polymer technology for underfill

AbstractCapillary type underfill is still the mainstream underfill for mass production flip chip applications. Flip chip packages are migrating to ultra low-k, Pb-free, 3D and fine pitch packages. Underfill selection is becoming more critical. This paper discusses the performance and potential of underfills using a novel organic-inorganic hybrid polymer technology.Compared to eutectic and high lead solder, tin-silver-copper solder has lower C.T.E., higher elasticity and greater brittleness. In light of these properties, it is generally better to select high Tg and lower CTE underfill in order to prevent bump fatigue during reliability testing. Given the brittleness of low-k dielectric layers of flip chips, the destruction of low-k layers by stress inside the flip chip packages has become a major issue. Underfills for low-k packages should have low stress, and the warpage should be small. It is expected that as the low-k trend expands, the underfill is required to provide less stress. Low Tg underfill shows lower warpage. New chemical technologies have been developed to address the needs of underfills for low-k/Pb-free flip chip packages, specifically organic-inorganic hybrid polymer compounds. The organic-inorganic hybrid polymer provides excellent cure properties which enable a balanced combination of low stress and good bump protection. The material properties of the underfill were characterized using Differential Scanning Calorimetry (DSC), Thermo-Mechanical Analysis (TMA), and Dynamic Mechanical Analysis (DMA). A daisy-chained test vehicle was used for reliability testing. A detailed study is presented on the underfill properties, reliability data, as well as finite element modeling results.

HIGH RELIABILITY HIGH MELTING LEAD-FREE MIXED BIAGX SOLDER PASTE SYSTEM

In the current work, a mixed solder powder BiAgX solder paste system with the melting temperature above 260°C and the comparable or even better reliability to the high lead solders has been studied. The mixed solder powder paste system is composed of a high melting first alloy solder powder as majority and the additive solder powder as minority. The additive solder is designed to react aggressively with various surface finish materials before or together with the melting of the majority solder to form a controllable IMC layer. The IMC layer of the mixed powder system is controllable by the species and the quantity of the additive solder and it is observed to be insensitive to thermal aging and thermal cycling in current tests while the high lead ones do show a considerable increase in IMC layer thickness. Microstructure investigation shows the fishbone shape IMC layer interlocks the bonding interface between solder and components. Both micron-sized and nano-sized Ag-rich precipitations in the joints have been observed to be well distributed in the joint. The exposed Ag-rich particles and the surrounding stepwise pattern in Bi matrix on the fracture surface indicate that these Ag-rich particles constrain the dislocation movement in Bi matrix thus enhance the strength and the ductility of the joint. Under thermal aging and thermal cycling, both the micron-sized and nano-sized Ag-rich precipitations exhibit only discernible and localized coarsening. The stable interfacial IMC together with the existence of the well dispersed Ag-rich particles are attributed to the promising reliability in BiAgX solder paste system.

Packaging Approach for Integrating 40/45-nm ELK Devices Into Wire Bond and Flip-Chip Packages

There is a rapid transition in the semiconductor packaging industry of devices moving toward 40/45-nm extreme low k (ELK) from the development phase into mainstream semiconductor assembly manufacturing. The drive to achieve adoption without major changes to process and equipment infrastructure while meeting the superior yield necessary is high. The main goal of this paper is to share learning's and provide solutions for integration and qualifications of 40/45-nm ELK devices into flip-chip (FC) and wire-bond (WB) package technology. The scope of this paper covers the fine-pitch ball grid array for the WB packages and FC chip-scale package for the FC Devices. The main challenge and focus point for WB 45/40-nm interconnects is on the first bond process. This paper will share some detailed analysis on the following. 1) Characterization for 45 nm ELK ultrafine-pitch. 2) Key factors for good Au ball bond integrity. 3) Recommendations for achieving the required levels of reliability for 45-nm Cu ELK. The challenge of FC Technology today has been changing at a faster rate and more and more adoption has been made from the conventional eutectic solder bumps or high lead solder bumps toward the lead free solder bump mainly due to the Green initiatives. This paper will share analysis on the following areas. 1) Thermo-mechanical simulation on key input factors and its correlation to actual evaluations. 2) Integration of Pb Free ELK bumps with 40-nm ELK technology are various critical processes. 3) Moldable underfill technology for Pb Free + ELK devices. In addition, critical process control is also required at the wafer level process of wafer thinning and dicing, including the need of Laser Grooving will also be covered.

High-lead flip chip bump cracking on the thin organic substrate in a module package

Flip chip bump cracking was observed after Si die attach reflow on the organic substrate of a module package. High-lead bump and eutectic SnPb cladding were used on Si die and the substrate sides, respectively. The reflow peak temperature was 260 °C for compatibility with passive components attach using lead-free solder. Flip chip bump cracking occurred at high-lead solder close to the die side. The cracking was eliminated by lowering the reflow peak temperature down to 225 °C. Main cause of the cracking at 260 °C reflow was attributed to the extensive Sn diffusion into high lead bump. This decreased the melting point of the high-lead solder around the die side, which in turn worsened the adhesion between solder and die due to the coexistence of solid and liquid. Diffusion length estimation showed both of the liquid- and solid-state diffusions of Sn. Crack gap in the solder bump was consistent with thermal expansion mismatch between Si die and organic substrate. The bump cracking was mitigated by use of 225 °C reflow, limiting Sn diffusion and providing a good integrity of high lead bumps on die side.

High Melting Temperature Lead Free Solder for Die Attach Application

Two lead free solders were developed for die attach application. The bismuth based solder has a melt temperature of 271C and thermal conductivity of 18W/mK. The zinc based solder has a melt temperature of 337C and thermal conductivity of 85W/mK. Both solders have acceptable wetting on bare copper and nickel plated copper substrate, could be processed using modified high lead solder process condition and survived 260C board level reflow simulation. This paper discusses the solder material properties, and presents the die attach process and reliability test results in a manufacturing environment.

High-temperature lead-free solder alternatives

For lead-free solders in the high-temperature regime, unfortunately, a limited number of alloying systems are available. These are Bi based alloys, gold involving alloys and Zn–Al based alloys. Based on these systems, possible candidate alloys were designed to have a melting range between 270 °C and 350 °C. Each has its own superior characteristics as well as some drawbacks however none of them can fulfill all the requirements to replace the current high-lead content solders. Even the alternative technologies that are currently being developed cannot address several critical issues of high-temperature soldering. Therefore, further research and development of high-temperature lead-free soldering is obviously needed.

Ultra Heat-Shock Resistant Die Attachment for Silicon Carbide With Pure Zinc

An ultra heat-shock resistant die-attach structure for a silicon carbide power device was developed. A silicon carbide die with a gold/titanium nitride coating was soldered with pure zinc onto a DBC with a silicon nitride insulator plate. This die-attach structure could resist severe thermal shock in air temperatures between -50°C and 300°C. No substantial change in microstructure was observed at the soldering interface, while conventional high-lead solder forms severe cracking. This die-attach structure can be also applied to other types of high-temperature device applications.

Effects of Ni Additions on the Growth of Cu3Sn in High-Lead Solders

In reactions between solders and Cu, additions of minor alloying elements, such as Fe, Co or Ni, to solders often reduce the Cu3Sn growth rate. Nevertheless, the mechanism for this effect remains unresolved. To provide more experimental observations that are essential for uncovering this mechanism, growth of Cu3Sn in the reaction between Cu and high-lead solders with or without Ni additions has been studied. The solders used for this study were 10Sn-90Pb and 5Sn-95Pb doped with 0 wt.%, 0.03 wt.%, 0.06 wt.%, 0.1 wt.% or 0.2 wt.% Ni. Reaction conditions included one reflow at 350°C for 2 min and solid-state aging at 160°C for up to 2000 h. The effect of Ni on the growth of Cu3Sn is discussed in detail based on the experimental results.

Interaction Between Ni and Cu Across 95Pb-5Sn High-Lead Layer

Ni/95Pb-5Sn/Cu ternary diffusion couples were used to investigate the cross-interaction between Ni and Cu across a layer of 95Pb-5Sn solder. High-lead solder layers with a thickness of 100 μm or 400 μm were electroplated over Cu foils. A pure Ni layer (20 μm) was then deposited over the as-deposited high-lead solder surface. The diffusion couples were then aged at 150°C to 250°C for different periods of time. With this technique, the diffusion couples were assembled without experiencing any high-temperature process such as reflow, which would have accelerated the interaction and caused difficulties in analysis. This study revealed that massive spalling also occurred during aging even though reflow was not used. The massive spalling began with the formation of microvoids. When the microvoids had congregated into large enough voids, intermetallic compounds (Cu3Sn) started to spall from the interface. This spalling phenomenon occurred sooner with increasing temperature and decreasing solder volume.

Design of lead-free candidate alloys for high-temperature soldering based on the Au–Sn system

Au–Sn based candidate alloys have been proposed as a substitute for high-lead content solders that are currently being used for high-temperature soldering. The changes in microstructure and microhardness associated with the alloying of Ag and Cu to the Au rich side as well to the Sn rich side of the Au–Sn binary system were explored in this work. Furthermore, the effects of thermal aging on the microstructure and microhardness of these promising Au–Sn based ternary alloys were investigated. For this purpose, the candidate alloys were aged at a lower temperature, 150 °C for up to 1 week and compared with aging at 200 °C for respective durations. It was determined in this work that the candidate alloys on the Sn rich side were relatively more stable, i.e. only the aging temperature had a substantial impact on the microstructure and not the aging duration. The candidate alloys aged at 200 °C were substantially softer on the Au rich side than the candidate alloys on the Sn rich side. However, the difference in hardness narrowed down considerably between the candidate alloys on the Au rich side and the Sn rich side when subjected to aging at 150 °C.

Design, assembly and reliability of large die and fine-pitch Cu/low- k flip chip package

This paper reports the design, assembly and reliability assessment of 21 × 21 mm 2 Cu/low- k flip chip (65 nm node) with 150 μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low- k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low- k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL. By integrating PEDL to the Cu/low- k chip, the reliability performance of the flip chip package has been improved by almost two times. This paper has demonstrated Moisture Sensitivity Test-Level 2 (MST-L2) qualified large die and fine-pitch Cu/low- k flip chip package. The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/low- k generations.

Comparative Study of Different Underfill Material on Flip Chip Ceramic Ball Grid Array Based on Accelerated Thermal Cycling

Problem statement: This study mainly to study the effect of several commercial underfill materials to the reliability of HiCTE Flip Chip Ceramic Ball Grid Array (FC-CBGA) package due to Accelerated Thermal Cycling (ATC) effect. Approach: The warpage condition of package, die back stress, interfacial die shear stress, and solder bump fatigue for different commercial underfills were assessed and compared via a commercial Finite Element Analysis (FEA) under JEDEC Standard of ATC. The thermo-mechanical properties of underfills for simulation were obtained by using Thermal Mechanical Analyzer (TMA) and Dynamic Mechanical Analyzer (DMA). The actual package of HiCTE FC-CBGA were assembled with those underfill materials and underwent ATC to be compared with FEA result. Results: The results from FEA and experimental were discussed to characterize the performance of each underfill material. The results of this study indicate that the underfill materials investigated, those with a glass transition temperature (Tg) and a Young’s modulus of approximately above 105°C and 8-9 GPa, respectively, were appropriate for HiCTE FC-CBGA with high lead solder bumps. Conclusion: The result from FEA analysis and ATC reliability test found that the underfill materials with high and medium low Young’s modulus has high reliability in FC-CBGA package.

Development of Au–Ge based candidate alloys as an alternative to high-lead content solders

Au–Ge based candidate alloys have been proposed as an alternative to high-lead content solders that are currently being used for high-temperature applications. The changes in microstructure and microhardness associated with the addition of low melting point metals namely In, Sb and Sn to the Au–Ge eutectic were investigated in this work. Furthermore, the effects of thermal aging on the microstructure and its corresponding microhardness of these promising candidate alloys have been extensively reported. To investigate the effects of aging temperature, candidate alloys were aged at a lower temperature, 150 °C for up to 3 weeks and compared with aging at 200 °C. After being subjected to high-temperature aging, the microstructure varied a lot in morphology in the case of both Au–Ge–Sb and Au–Ge–Sn candidate alloys while the microstructure remained relatively stable even after long-term thermal aging in the case of the Au–Ge–In candidate alloy. The microhardness measurement is well correlated with the solubility and reactivity of these alloying elements, characteristics of their intermetallic compounds (IMCs) and the distribution of phases. The primary strengthening mechanism in the case of Au–Ge–In and Au–Ge–Sn combinations was determined to be the classic solid solution strengthening. The Au–Ge–Sb combination was primarily strengthened by the refined (Ge) dispersed phase. The aging temperature had a significant influence on the microhardness in the case of the Au–Ge–Sn candidate alloy. The distribution of phases played a relatively more crucial role in determining the ductility of the bulk solder alloy. The findings of this work are: the addition of Sb to the Au–Ge eutectic would not only decrease its melting point but would also improve its ductility substantially and the lattice strains induced by the In atoms were the most effective strengthening mechanism.

Fundamental Study of the Intermixing of 95Pb-5Sn High-Lead Solder Bumps and 37Pb-63Sn Pre-Solder on Chip-Carrier Substrates

This study investigated the intermixing of 95Pb-5Sn solder bumps and 37Pb-63Sn pre-solder in flip-chip solder joints. The reaction conditions included multiple reflows (up to ten) at 240°C, whereby previously solder-coated parts are joined by heating without using additional solder. We found that the molten pre-solder had an irregular shape similar to a calyx (i.e., a cup-like structure) wrapped around a high-lead solder bump. The height to which the molten pre-solder ascended along the solid high-lead solder bump increased with the number of reflows. The molten pre-solder was able to reach the under bump metallurgy (UBM)/95Pb-5Sn interface after three to five reflows. The molten pre-solder at the UBM/95Pb-5Sn interface generated two important phenomena: (1) the molten solder dewetted (i.e., flowed away from the soldered surface) along the UBM/95Pb-5Sn interface, particularly when the number of reflows was high, and (2) the molten pre-solder transported Cu␣atoms to the UBM/95Pb-5Sn interface, which in turn caused the Ni-Sn compounds at the chip-side interface to change into (Cu0.6Ni0.4)6Sn5.

Decapsulation Method for Flip Chips with Ceramics in Microelectronic Packaging

The decapsulation of flip chips bonded to ceramic substrates is a challenging task in the packaging industry owing to the vulnerability of the chip surface during the process. In conventional methods, such as manual grinding and polishing, the solder bumps are easily damaged during the removal of underfill, and the thin chip may even be crushed due to mechanical stress. An efficient and reliable decapsulation method consisting of thermal and chemical processes was developed in this study. The surface quality of chips after solder removal is satisfactory for the existing solder rework procedure as well as for die-level failure analysis. The innovative processes included heat-sink and ceramic substrate removal, solder bump separation, and solder residue cleaning from the chip surface. In the last stage, particular temperatures were selected for the removal of eutectic Pb-Sn, high-lead, and lead-free solders considering their respective melting points.

Analysis and Prediction of Vibration-Induced Solder Joint Failure for a Ceramic Column Grid Array Package

Solder joint fatigue failure under vibration loading continues to be a concern in microelectronic industry. Existing literature has not adequately addressed high-cycle fatigue failure of high-lead solder joints, especially under a broad spectrum of vibration frequencies. Also, damage mapping across solder joints in an area-array package has not been effectively studied using numerical models and experimental cross sectioning. This paper aims to develop an experimental and modeling approach that can accurately determine the solder joint behavior of electronic components under vibration conditions. In particular, this paper discusses the out-of-plane sinusoidal vibration experiments at 1G, numerical modeling, and fatigue life prediction for a 42.5×42.5×4mm3 1089 input∕output ceramic column grid array (CCGA) package on a 133×56×2.8mm3 FR4 board. Detailed investigation and characterization involving dye-and-pry analysis, microstructural examination, and numerical modeling enabled the development of a high-cycle stress-based equation for lead-containing CCGA under sinusoidal loading. The developed approach has been applied to a number of cases including a CCGA package with a heat sink as well as a CCGA package subjected to frequency sweeps. It is seen that the predictions from the developed model agree well with experimental data and that the developed model can map the evolution of solder damage across all solder joints and can also provide important design recommendations in terms of solder joint location as well as heat sink attachment.

Reliability of high temperature solder alternatives

European RoHS directives, enacted in response to concerns about the toxicity of lead, are driving the substitution of Pb-free solders for Pb-containing solders at the component to board level. While European RoHS regulations currently exempt high Pb solders used as component solders and die attaches for automotive and other high temperature applications, there is a strong drive to find Pb-free alternatives for these high temperature electronic applications, as well. This paper presents constitutive and reliability information on one of the widely used high lead solder materials as a baseline, and discusses potential alternative technologies for high temperature solders with the goal of identifying a cost-effective lead-free solder that can be used at temperatures greater than 200 °C.

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

Solid-state annealing behavior of two high-Pb solders, 95Pb5Sn and 90Pb10Sn, on Cu under bump metallurgy

The solid-state annealing behavior of two high-lead solders, 95Pb5Sn and 90Pb10Sn (in wt.%), was examined. After reflow, Cu3Sn intermetallics formed on the Cu under bump metallurgy (UBM) for both solder alloys. However, solidstate annealing produced significantly different reaction morphologies for the two solder compositions. The Cu3Sn intermetallics spalled off faster at higher temperatures in the 95Pb5Sn solder. In the case of 90Pb10Sn solder, the Cu3Sn intermetallics continued to grow even after 1500 h at 170°C. The difference was explained by a two-step phenomenon—Sn diffusion from the bulk solder region to the solder/Cu3Sn interface (JSn), and subsequent intermetallic formation (ICu3Sn) by interdiffusion of Cu and Sn. For 95Pb5Sn, the relation, JSn ICu3Sn was suggested for the continuous intermetallic growth of the 90Pb10Sn solder. Although a small difference was expected between the two quantities in both solder alloys, the difference in the solid-state annealing behavior was dramatic.