High Field-effect Mobility Research Articles

Programmed Design of Highly Crystalline Organic Semiconductor Patterns with Uniaxial Alignment via Blade Coating for High-Performance Organic Field-Effect Transistors.

A solution-printing technique that enables the patterning and aligning of organic semiconducting crystals is necessary for their practical application. Here, we report the facile growth of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PEN) semiconducting crystal patterns via a novel blade-coating technique. Defining low/high shearing-speed regions alternatively in a programmed manner enables the growth of TIPS-PEN crystals in low-speed regions and their patterning in high-speed regions. Various crystal-analysis tools, including polarized UV-vis absorption spectroscopy, grazing-incidence wide-angle X-ray scattering, and near-edge X-ray absorption fine structure, reveal that a crystal grown at an optimum shearing speed is highly oriented along the shearing direction with high crystallinity, and its molecules have a more edge-on orientation for efficient lateral-charge transport. As a result, organic field-effect transistors comprised of these crystals show a high field-effect mobility of up to 1.74 cm2/(V s). In addition, various crystal patterns can be created by simply changing the programming parameters, suggesting the broad utility of the crystal patterns and printing technique.

Amorphous Tin Oxide Applied to Solution Processed Thin-Film Transistors.

The limited choice of materials for large area electronics limits the expansion of applications. Polycrystalline silicon (poly-Si) and indium gallium zinc oxide (IGZO) lead to thin-film transistors (TFTs) with high field-effect mobilities (>10 cm2/Vs) and high current ON/OFF ratios (IOn/IOff > ~107). But they both require vacuum processing that needs high investments and maintenance costs. Also, IGZO is prone to the scarcity and price of Ga and In. Other oxide semiconductors require the use of at least two cations (commonly chosen among Ga, Sn, Zn, and In) in order to obtain the amorphous phase. To solve these problems, we demonstrated an amorphous oxide material made using one earth-abundant metal: amorphous tin oxide (a-SnOx). Through XPS, AFM, optical analysis, and Hall effect, we determined that a-SnOx is a transparent n-type oxide semiconductor, where the SnO2 phase is predominant over the SnO phase. Used as the active material in TFTs having a bottom-gate, top-contact structure, a high field-effect mobility of ~100 cm2/Vs and an IOn/IOff ratio of ~108 were achieved. The stability under 1 h of negative positive gate bias stress revealed a Vth shift smaller than 1 V.

Material Design of New p-Type Tin Oxyselenide Semiconductor through Valence Band Engineering and Its Device Application.

This paper reports a new p-type tin oxyselenide (SnSeO), which was designed with the concept that the valence band edge from O 2p orbitals in the majority of metal oxides becomes delocalized by hybridizing Se 4p and Sn 5s orbitals. As the Se loading increased, the SnSeO film structures were transformed from tetragonal SnO to orthorhombic SnSe, which was accompanied by an increase in the amorphous phase portion and smooth morphologies. The SnSe0.56O0.44 film annealed at 300 °C exhibited the highest Hall mobility (μHall), 15.0 cm2 (V s)-1, and hole carrier density (nh), 1.2 × 1017 cm-3. The remarkable electrical performance was explained by the low hole effective mass, which was calculated by a first principle calculation. Indeed, the fabricated field-effect transistor (FET) with a p-channel SnSe0.56O0.44 film showed the high field-effect mobility of 5.9 cm2 (V s)-1 and an ION/OFF ratio of 3 × 102. This work demonstrates that anion alloy-based hybridization provides a facile route to the realization of a high-performance p-channel FET and complementary devices.

Investigation of Multi-Level Cell Characteristic in Amorphous Indium-Gallium-Zinc Oxide Thin-Film-Transistor Based 1T-1R Non-Volatile Memory Device.

In this work, we have implemented nonvolatile resistive random access memory (ReRAM) cells consisting of one transistor (1T) and one resistor (1R) configuration by integrating a high-performance InGaZnO (IGZO) thin-film-transistor (TFT) and an HfO₂ resistive switching component on a single substrate for system-on-panel (SoP) technology. ReRAM cells with a 1T-1R configuration can reduce undesired crosstalk caused by leakage current between adjacent memory cells. The a-IGZO TFTs used for 1T-1R integration showed excellent electrical characteristics with a high field-effect mobility of 10.8 cm²/V s, a low subthreshold swing of 226 mV/dec and a large on-off current ratio of 9.2 × 107. The 1T-1R integrated memory cells exhibited BRS behavior, uniform distribution of resistance states and operating voltage, stable DC endurance and reliable data retention characteristics. In addition, we obtained MLC characteristics in a 1T-1R integrated memory cell by controlling the driving current with the gate voltage of a-IGZO TFTs. In multi-level operation, it showed a low operating voltage of 1 V, stable endurance and reliable retention characteristics at 85 °C.

High Field Effect Mobility, Amorphous In-Ga-Sn-O Thin-Film Transistor With No Effect of Negative Bias Illumination Stress

We report a dual-gate, amorphous In-Ga-Sn-O (a- IGTO) thin-film transistor (TFT) exhibiting high field-effect mobility ( $\mu _{\text {FE}}$ ) and very low subthreshold swing. The TFT has a bottom-gate having $5~ \mu \text{m}$ overlap with source/drain (S/D) and a top-gate with $0.5~\mu \text{m}$ offset with S/D electrodes. The bottom-gate potential is swept at various top-gate voltages. The $ \mu _{\text {FE}}$ of a-IGTO TFT is found to be 39.1 cm $^{\text {2}}\text{V}^{-\text {1}}\text{s}^{-\text {1}}$ which is almost independent of top-gate potential. The subthreshold swing is ~0.19 Vdec−1 and also does not change much with top-gate potential variation between −50 V and +90 V, indicating very low density of states in the gap. The a-IGTO TFT exhibits no effect of negative bias illumination stress.

(Invited) Single-Crystalline Silicon CMOS Fabrication on PET By Meniscus Force Mediated Layer Transfer Technique

Fabrication of single-crystalline silicon CMOS circuits on a polyethylene terephthalate (PET) substrate has been carried out by meniscus force mediated layer transfer (MLT) at a very low temperature of 130°C. New cleaning process, self-limit etching, and high-energy ion implantation are the key for simultaneous transfer of both n- and p-channel islands to PET substrate. Transfer of SOI [p-type (100), 8–20 Wcm, 80-nm-thick] islands by MLT and CMOS fabrication process on a PET substrate are schematically summarized in Fig. 1. To form the “mid-air cavity”, SOI layer is patterned to dog-bone shaped channel islands (Fig. 1(a)). After ion implantation in the channel, source, and drain (S/D) regions and activation of impurities at 1000°C (Fig. 1(b)), 400-nm-thick buried oxide (BOX) layer underneath is etched by 25% hydrofluoric acid at 30°C to form thin SiO2 pillars that support the SOI layer above the mid-air cavity (Fig. 1(c)). Here, a pillar shaping implantation (PSI) was newly introduced to control the pillar shape. In addition, to precisely control the pillar size, self-limited etching technique was also introduced. Introduction of these two processes improved the layer transfer yield significantly, as mentioned later. Conformal thermal oxidation of the SOI layers is performed in dry oxygen at 1000 °C to form 11 nm SiO2 (Fig. 1(d)). The top oxide layer works as a barrier layer against contamination from the PET substrate, and the bottom oxide layer works as the gate insulator of the MOSFETs. The PET substrate is firstly aged at 130 °C for 10 min to suppress thermal expansion and shrinkage during the CMOS fabrication process, followed by scrub cleaning to remove precipitates. The SOI wafer and counter PET substrate are in close face-to-face contact with filling water, and they are heated on a hot plate at 80 °C for 10 min (Fig. 1(e)). When these substrates are separated, the SOI islands are transferred by the meniscus force generated between the SOI layer and the PET substrate (Fig. 1(f)). After the contact holes are opened, the gate and S/D electrodes are formed by aluminum evaporation and wet etching (Fig. 1(g)). The maximum process temperature after MLT is 130 °C at the post-bake for the lithography of contact holes and Al electrodes. By the introduction of above mentioned new processes, we have successfully fabricated CMOS on PET. The transfer yield was 99.86%. MOSFETs on PET show very high field effect mobilities (µFE) of 603 cm2V-1s-1 (n) and 172 cm2V-1s-1 (p) and low subthreshold swings (S factors) of 75.3 mV/dec (n) and 72.0 mV/dec (p), respectively. They show an on/off ratio of larger than 107 (at Vd = 0.1 V) with low off current (<10-13 A). CMOS inverters showed clear input/output characteristics under a supply voltage (Vdd) of 2.0 V, and we obtained clear output signal of 5-stage ring oscillator (RO). High-speed operation of 14.6 MHz was achieved on PET. The oscillation frequency of the transferred RO on PET is about 3.5 times as high as that of non-transferred RO on SOI wafer. This is because the parasitic capacitance in the case of RO on PET is significantly small. Figure 1

Low-Voltage Metal-Oxide Thin Film Transistors Using P-Type Tin-Oxide Semiconductors.

In this paper, the effect of channel annealing and oxygen flow rate in P-type tin-monoxide (SnO) thin film transistor (TFT) was investigated to reach the process compatibility with n-type oxide-based TFT. The optimized P-type SnO TFT with a small threshold voltage of -0.1 V, a high field-effect mobility of 4 cm² V-1 s-1 and an on/off current ratio of >10² was proposed. From the experimental results, the 150 °C channel annealing revealed a metallic behavior but a semiconductor-like property at a higher 200 °C that was favorable for transistor rectification. Besides, the higher oxygen flow rate was also helpful for improving device mobility and driving current, but shows a slight increase in off-state leakage, which is unavoidable due to the increase of grain in SnO channel.

Improved performance of top-gated multilayer MoS2 transistors with channel fully encapsulated by Al2O3 dielectric

Multilayer two-dimensional molybdenum disulfide (MoS2) field-effect transistors with Al2O3 or HfO2 as top gate dielectric and bottom passivation layer have been comparatively studied. The top-gated MoS2 transistor with Al2O3 as both top gate dielectric and bottom passivation layer exhibits excellent electrical characteristics with an on-off ratio of ∼106, a subthreshold swing of 97 mV dec−1, a low interface-trap density of 1.66×1012 cm−2eV−1, and a high field-effect mobility of 105 cm2 V−1 s−1. All these should be attributed to superior interface quality between Al2O3 top gate dielectric and MoS2, and enhanced dielectric screening effect due to Al2O3 bottom passivation layer.

Solution Processed AlInO/In2O3 Heterostructure Channel Thin Film Transistor with Enhanced Performance

AbstractThin film transistors (TFTs) with solution processed AlInO/In2O3 heterostructure channels are demonstrated with enhanced performance. TFTs with single AlInO channels with various Al concentrations are used for comparison. Appropriate concentrations of Al in AlInO single layer can slightly improve the TFT performance. For the AlInO layer with Al concentration higher than 20%, the resistance is so large that no typical transfer characteristics are observed. In contrast, the overall performances are greatly improved using the AlInO/In2O3 heterostructure channel. High field effect mobility is achieved greater than 40 cm2 V−1 s−1 with a sub threshold slope of 0.7 V decade−1 and on/off ratio of 107 from the heterostructure TFT with a AlInO (30%) top layer. The mobility is affected by the tunnel contact series resistance, which can be modulated by the thickness of the AlInO layer. The enhanced field effect mobility is attributed to the formation of 2D electron gas confined at the AlInO/In2O3 interface, which results in a bulk accumulation effect. Finally, improved positive bias stress stability is obtained by inducing the AlInO top layer with a strong AlO bond. The as investigated results show a very promising future for oxide thin film transistor performance enhancements via heterostructure engineering.

Stable InSe transistors with high-field effect mobility for reliable nerve signal sensing

Among two-dimensional layered semiconductors, indium selenide (InSe) is one of the most promising materials with absolute advantages in field-effect transistors (FETs) because of its high electron mobility and stable material properties. Some work has been performed to improve the mobility of InSe FETs. However, in practical applications, electrical stability of FETs is another essential factor to guarantee the performance of the electronic system. Here, we show a highly stable InSe FET with a field-effect mobility of 1200 cm2/V·s in the practical working regime. The bottom-gate staggered InSe FET was fabricated with a polymethyl methacrylate (PMMA)/HfO2 dual-layer gate dielectric and PMMA back-channel encapsulation. The hysteresis was maintained at 0.4 V after 30 days of storage under normal ambient conditions, and the threshold voltage shift was retained at 0.6 V with a gate stress VGS of 10 V, which represents the best electrical stability reported to date. Its high mobility and electrical stability enable reliable detection of the weak nerve action potential at a low power consumption. High-performance InSe FETs expand their promising applications in flexible and in situ real-time intelligent nerve action potential recording.

Amorphous Si–Zn–Sn–O Thin Film Transistor with In–Si–O as Transparent Conducting Electrodes

We revealed a novel method to fabricate amorphous silicon-zinc-tin-oxide (a-SZTO) thin-film transistors (TFTs) has been reported with transparent Indium–silicon–oxide (ISO) source/drain (S/D) electrodes. The presented TFTs exhibited a high field-effect mobility of 14.65 cm2/Vs, a threshold voltage of 2.87 V, and a low subthreshold swing of 0.39 V/decade. It is suggested that the small work function of ISO (4.49 eV) compared to that of a-SZTO (4.53 eV) induces an ohmic contact at the ISO/SZTO junction, which makes it possible the effective injection of electrons from oxide materials into the a-SZTO semiconductor. Determine the stability of a-SZTO TFTs under Negative bias temperature stress (NBTS) was measured ∆VTH = 1.21 V at 333 K, and − 20 V for 7200 s.

Atomically Thin Ga2S3 from Skin of Liquid Metals for Electrical, Optical, and Sensing Applications

Intriguing physical and chemical properties of atomically thin semiconductors provide avenues for the development of the next-generation electronics, optoelectronics, and sensing applications. However, many materials are intrinsically nonlayered and therefore difficult to obtain in two dimensions (2D) due to the presence of strong in-plane bonds. Here, we adopted liquid metal synthetic strategies to produce 2D gallium sulfide (Ga2S3), which is an intrinsically nonlayered material. The obtained monoclinic α-Ga2S3 has a relatively high field-effect mobility of 3.5 cm2 V–1 s–1 and features a p-type material with a bandgap of 2.1 eV. Photodetectors that are made based on these synthesized 2D Ga2S3 exhibit relatively strong photodetectivity of 1010 jones and photoresponsivity of 240 A W–1 in visible wavelengths. The 2D Ga2S3 is also found to be suitable for sensing of nitrogen dioxide (NO2) gas at low evaluated temperatures. Excellent electronic, optical, and gas sensing performance demonstrated in this work offers great promises for synthesizing high quality 2D materials based on the liquid metal framework.

Solution-processed undoped and Indium doped ZnO thin film transistors: role of Ag nanowires into InZnO channel layer

We report solution-processed undoped ZnO, 1 at% In doped ZnO (IZO) and 1 at% Ag nanowires (AgNWs) embedded IZO thin film transistors (TFTs). The mobility of prepared TFTs was enhanced compared to undoped ZnO, and AgNWs embedded IZO TFT exhibited excellent electrical performances with high field-effect mobility of 38.17 cm2V−1s−1 and high on/off current ratio on the order of 107. The energy dispersive x-ray (EDX) elemental mapping and x-ray photon spectroscopy (XPS) analysis demonstrated that the Ag particles are diffused into IZO thin film from AgNWs, suggesting that AgNWs played dual role in the channel layer which served as an acceptor charge carrier and a conductive path for charge carriers. SEM images showed that IZO film had increased grain size in comparison to undoped ZnO film and that AgNWs were well interconnected IZO film. The increment in the grain size in the IZO film and well connected AgNWs in the IZO films lead to enhanced mobility of the TFTs.

The new route for realization of 1‐μm‐pixel‐pitch high‐resolution displays

AbstractA new pixel structure for the realization of a 1‐μm‐pixel‐pitch display was developed. This structure, named vertically stacked thin‐film transistor (VST), was based on the conventional back‐channel etched thin‐film transistor (TFT), but all the layers except the horizontal gate line were vertically stacked on the embedded data line, enabling the implementation of high‐resolution display panels. The VST device with a channel length of 1 μm showed a high field effect mobility of more than 50 cm2/Vs and low subthreshold slope of 78 mV per decade. It also shows a high uniform electrical characteristic over the entire 6‐in. wafer. The development of a new pixel architecture is expected to enable the implementation of 1‐μm‐pixel‐pitch high‐resolution displays such as spatial light modulators for digital holograms.

Delta-doped SrTiO3 top-gated field effect transistor

Oxide heterostructures are an attractive platform for incorporation in field-effect transistors (FETs) due to their diverse physical properties which can be tuned by electrostatic gating. We report a top-gated FET based on a SrTiO3 delta-doped structure, which operates down to cryogenic temperatures. The device shows excellent DC characteristics with an on/off ratio greater than 104 and field effect mobility estimated to be 2125 cm2/V s at 2 K. The high field effect mobility was consistent with the Hall mobility and is attributed to the formation of a two-dimensional electron system in the delta-doped layer: two-dimensional gate-tunable Shubnikov-de Haas oscillations confirm this. The achievement of an electron density of 3 × 1012 cm−2 in a gate-tunable geometry allows for the exploration of the interplay between magnetic, ferroelectric, and superconducting properties of SrTiO3 in the quantum limit.

Performance Enhancement for Tungsten-Doped Indium Oxide Thin Film Transistor by Hydrogen Peroxide as Cosolvent in Room-Temperature Supercritical Fluid Systems.

In this study, hydrogen peroxide (H2O2) cosolvent, which was dissolved into supercritical-phase carbon dioxide fluid (SCCO2), is employed to passivate excessive oxygen vacancies of the high-mobility tungsten-doped indium oxide without any essential thermal process. With the detailed material analysis, the internal physical mechanism of the cosolvent effect or the interaction between the cosolvent solution and supercritical-phase fluid is well discussed. In addition, the optimized result has been applied for the thin film transistor device fabrication. As a result, the device with SCCO2 + H2O2 treatment exhibits the lowest subthreshold swing of 82 mV/dec, the lowest interface trap density of 8.76 × 1011 eV-1 cm-2, the lowest hysteresis of 47 mV, and an excellent reliability and uniformity characteristic compared with any other control groups. Besides, an extremely high field-effect mobility of 98.91 cm2/V s can also be observed, while there is even a desirable positive shift for the threshold voltage. Notably, compared with the untreated sample, the highest on/off current ratio of 5.11 × 107 can be achieved with at least four orders of magnitude enhancement by this unique treatment.

Low-Temperature Processed Tin Oxide Transistor With Ultraviolet Irradiation

Using a novel ultraviolet (UV) irradiation method, we processed a high-performance thin-film transistor (TFT) at low temperatures. Satisfactory device integrity that was demonstrated by high field-effect mobility values of 92 and 43 cm2/Vs, small subthreshold slopes of 74 and 81 mV/decade, and ON-current/ OFF-current values of $3\times 10^{6}$ and $7\times 10^{5}$ was achieved for the SnO2 TFT at low processing temperatures of 180 °C and 100 °C, respectively. The results of X-ray photoelectron spectroscopy showed that the UV irradiation considerably increased the presence of Sn4+ and reduced the presence of unwanted Sn2+, even at low processing temperatures, improving the quality of SnO2.

23‐3: Distinguished Paper: The New Route for Realization of 1µm‐pixel‐pitch High Resolution Displays

We present a new pixel structure to realize the 1μm‐pixel‐pitch display. This structure is based on the conventional back‐channel etched thin‐film transistor (TFT), but all layers except the horizontal gate line are vertically stacked on the embedded data line, enabling the implementation of high resolution display panels. The vertically‐stacked TFT with 1μm‐channel length shows a high field effect mobility over 50 cm2/Vs, low subthreshold slope of 78 mV/decade. It also shows a high uniform electrical characteristic over the entire 6‐inch wafer. The development of new architecture enables the implementation of a 1μm‐pixel‐pitch high resolution displays such as digital hologram.

Multiple-layer black phosphorus phototransistor with Si microdisk resonator based on whispering gallery modes

In this study, we investigate the whispering gallery modes (WGMs) of a 14-layer black phosphorous (BP) phototransistor based on a silicon microdisk. The transmission characteristics of the waveguide-coupled microdisk resonator with and without BP are analyzed to determine the resonance wavelength. The effect of BP on the electric field distributions of the WGMs of the Si microdisk resonator is simulated by using the finite-element method. In addition, the enhanced optical absorption of the BP-covered Si microdisk resonator is further analyzed by the coupled mode theory. Contrastingly, the device also functions as a phototransistor with a peak responsivity of 328.1A/W and high field-effect mobility of nearly 466.6 cm2 V-1 s-1. Our proposed device paves the path for the exploitation of BP optoelectronics devices with the assistance of optical microresonators in the near-infrared range (NIR).

Stretchable Polymer Gate Dielectric by Ultraviolet-Assisted Hafnium Oxide Doping at Low Temperature for High-Performance Indium Gallium Tin Oxide Transistors.

This paper reports the fabrication of indium gallium tin oxide (IGTO) thin-film transistors (TFTs) with ultraviolet (UV)-treated PVP- co-PMMA-based hybrid gate insulators at an extremely low temperature (≤150 °C). Synergetic hafnia loading and UV treatment were used to tailor the mechanical softness and hydroxyl fraction in the polymer dielectric film. The UV-treated hybrid dielectric film had a low hydroxyl concentration, a smoother surface, and a denser packing nature, which can be explained by the high ionicity of hafnium oxide and photon-assisted improvement in the cohesion between organic and inorganic materials. Suitability of the UV-treated hybrid dielectric film as a gate insulator was evaluated by fabricating bottom gate TFTs with sputtered IGTO films as a channel layer, which showed high carrier mobility at a low temperature. The resulting IGTO TFTs with a UV-treated hybrid gate insulator exhibited a remarkable high field-effect mobility of 25.9 cm2/(V s), a threshold voltage of -0.2 V, a subthreshold gate swing of 0.4 V/decade, and an ION/OFF ratio of >107 even at a low annealing temperature of 150 °C. The fabricated IGTO TFTs with the UV-treated hybrid dielectric film on the plastic substrate were shown to withstand the 100 times mechanical bending stress even under an extremely small curvature radius of 1 mm due to the intrinsic stretchability of the hybrid dielectric film.