High-efficiency Doherty Power Amplifier Research Articles

A Ka-Band Watt-Level High-Efficiency Doherty Amplifier MMIC in 90-nm GaAs Technology

This letter presents a Ka-band watt-level high-efficiency Doherty power amplifier (DPA) monolithic microwave integrated circuit (MMIC) in 90-nm gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) technology. To realize the high efficiency of DPA at 6-dB power back-off (PBO), a low-loss compact Doherty output network is proposed to directly combine the matching network and the load modulation network (LMN) into a compact network. Then, the peaking amplifier of DPA is an optimized design to guarantee a sufficient load modulation at the 6-dB PBO level. The proposed DPA exhibits a measured saturation output power in the range of 29.5–30 dBm, with a corresponding peak power-added efficiency (PAE) in the range of 35%–40% from 26.5 to 30.5 GHz. Moreover, the PAE at the 6-dB PBO level of the proposed DPA is in the range of 25%–30.2% from 26.5 to 30.5 GHz.

Design of a C-Band High-Efficiency Doherty Power Amplifier With Harmonic Control

A design methodology of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$ </tex-math></inline-formula> -band high-efficiency Doherty power amplifier (DPA) with harmonic control is presented in this letter. The equivalent parasitic network (EPN) of the packaged device is constructed by a deembedding technique. The phase delay caused by the transistor parasitics is calculated using the scattering matrix of the EPN. Besides, the influence of the phase delay on DPA design is analyzed. To improve the efficiency at output back-off (OBO) power level, postmatching network (PMN) is used to control the second harmonic. A high-efficiency DPA working over 6.4–7.1 GHz is implemented, fabricated, and measured. The DPA delivers a saturation output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {sat}}$ </tex-math></inline-formula> ) of 39.6–41.6 dBm. Meanwhile, the drain efficiencies in the interested frequency band are 45.1%–53.2% and 34.5%–43.1% at the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {sat}}$ </tex-math></inline-formula> and 6-dB OBO power levels, respectively.

High efficiency Doherty power amplifier based on asymmetrical matching network

Doherty power amplifier (DPA) with high efficiency at the output power back off is highly demanded for modern wireless communication systems to achieve high data rates and reduce the power consumption and operation costs. This paper presents a new design strategy for enhancing DPA’s back-off efficiency. New design strategy called asymmetrical matching network is used to achieve asymmetric operation, which helps to compensate for the low power delivered by the peaking stage in the conventional DPA. The simulation results showed an enhancement in the back-off efficiency, where the proposed design is able toachieve 46-52% drain efficiency at 8 dB output power back-off while maintains high efficiency of 73-80 % at saturation over the designed bandwidth of 3.4-3.6 GHz. The proposed design is suitable for high efficiency sub-6 GHz fifth-generation wireless applications.&lt;br /&gt;&lt;div&gt; &lt;/div&gt;

A Broadband Doherty Power Amplifier With Hybrid Class-EFJ Mode

This paper proposes a method that employs novel hybrid continuous class-EFJ power amplifiers (PAs) as carrier PA to design a broadband high-efficiency Doherty power amplifier (DPA). Bandwidth characteristic of the proposed DPA is analyzed in detail. By proper selection of related parameter values, up to 78% fabrication bandwidth can be obtained. Post-harmonic tuning network is applied to improve the bandwidth and enhance the efficiency. Then, a closed design process is presented to design broadband DPA based on derived theories. For validation, a broadband DPA operating in 1.2-2.8 GHz is designed and fabricated. Measurements illustrate that the DPA can deliver saturated output power between 43.7 dBm and 44.1 dBm in 1.2-2.8 GHz, and the saturated drain efficiency from 60.5% to 74.2 % is achieved. Moreover, drain efficiency is 48.1%-57.6% at the 6 dB power back-off. Compared with conventional DPAs, the proposed DPA exhibits superior performance of bandwidth characteristics and power back-off efficiency over a wide bandwidth.

A 3.3–4.3-GHz High-Efficiency Broadband Doherty Power Amplifier

In this letter, the design of a broadband high-efficiency Doherty power amplifier (DPA) with a bandwidth of 1000 MHz for the 5G frequency band is proposed. The postmatching structure is employed to achieve broadband performance. The proposed DPA shows high efficiency at 6-dB output power back-off (OBO) in the entire 1000-MHz band. The DPA has been designed and implemented using commercial GaN HEMTs to validate the high efficiency and broadband characteristics. The fabricated DPA attains a measured 7.1–11.1-dB saturated gain and a 43.2–44.5-dBm saturated power. The 46%–52% and 58.6%–68.9% drain efficiencies are obtained at 6-dB OBO and saturation throughout the design band, respectively. A 20-MHz LTE modulated signal with a peak-to-average power ratio of 7.2 dB is also applied to the proposed DPA at 3.5 GHz. The average output power is 37.2 dBm. The measured ACPR is improved from −27 to −48.9 dBc with digital predistortion (DPD) performed.

A high-efficiency Doherty Power Amplifier for wireless base stations

ABSTRACT This paper presents a new high-efficiency two-way Doherty Power Amplifier (DPA) with a modified output matching structure for Wideband Code Division Multiple Access (W-CDMA) low-to-medium power base station applications. A blended design is proposed using the symmetrical topology of equal rated power amplifying devices with unequal output impedances for the carrier and peaking amplifier to achieve enhanced efficiency and desired linearity in 1900 MHz band. The proposed output circuit modifications encompass the usage of parasitic capacitor compensation technique for the carrier amplifier, optimum offset line along with the Doherty combiner to achieve high efficiency over 6 to 10 dB extended range of back-off operation. The measured results of the DPA demonstrate a Power Added Efficiency (PAE) of more than 49.9% at +34 dBm W-CDMA signal power, which is between 8 and 8.5 dB back-off from the peak power level of 42.2 dBm. The DPA has a large signal power gain of 13 dB at 1960 MHz. Further, the PAE is 39.5% and linearised Adjacent Channel Power Ratio (ACPR) is −46.2 dBc, both at 10 dB back-off from peak power. In these back-off power levels, this implementation provides significant efficiency improvement using symmetrical devices and with excellent linearity.

A Mixed Topology for Broadband High-Efficiency Doherty Power Amplifier

In this paper, a mixed topology for high efficiency, broadband Doherty power amplifier (DPA) is proposed. The transistor gate biases are set to deep Class-AB for the carrier device and deep Class-C for the peaking device, which enable the DPA to achieve its high efficiency. However, this biasing scheme leads to an inadequate back-off range, which in the past limited applicability. To compensate for this reduced back-off range, a “ $\pi $ -type” harmonic injection network (HIN) is integrated into the DPA thereby allowing the second harmonic to be injected between the two active devices. This achieves waveform engineering, which enhances the output power of the peaking amplifier. However, the use of this HIN leads to a reduction in bandwidth due to a mismatch at the fundamental frequency. A bandwidth compensation technique is then proposed, thereby reducing the peaking device drain impedance variation. This mitigates the reduction in bandwidth as a result of the HIN. A high-efficiency DPA is prototyped based on two identical 10-W gallium nitride HEMTs. Measurement results show that a drain efficiency of greater than 60% is achieved at 5.3–6-dB output back-off power from 1.4 to 2.1 GHz.

Bandwidth Extension of Doherty Power Amplifier Using Complex Combining Load With Noninfinity Peaking Impedance

In this paper, a high-efficiency Doherty power amplifier (DPA) using the complex combining load (CCL) with noninfinity peaking impedance for broadband operation is presented. By applying the CCL, the load impedance of the carrier amplifier at saturation power level can be compensated at different operation frequencies. Considering the influences of the output impedance of the peaking PA on the carrier PA, a detailed analysis of the optimal noninfinity peaking output impedance with the CCL is carried out on the whole operation frequency range. Theoretical analysis of the output power and drain efficiency (DE) reveals that the CCL can offer a new degree of freedom for extending the bandwidth of the DPA. Based on the proposed theory, a modified DPA working over the frequency band of 1.1-2.4 GHz (bandwidth of 74%) is designed and fabricated based on GaN HEMT devices. Experimental results exhibit 6-dB output back-off drain efficiencies of 43.8%-54.9% and saturated drain efficiencies of 55.4%-68% can be obtained. The saturated output power of the DPA is 43.3-45.4 dBm with a gain of 9.5-11.1 dB across the whole operation band. When driven with long-term evolution modulated signals with 6.5-dB peak-to-average power ratio, the DPA exhibits an adjacent channel leakage ratio better than -49 dBc while maintaining a DE of 44% after digital predistortion linearization.

Design of a broadband high-efficiency Doherty power amplifier for 5G communication systems

Design of a broadband high-efficiency Doherty power amplifier for 5G communication systems

A highly extended high-efficiency range Doherty power amplifier for high PAPR communication signals

In this paper, design, simulation and fabrication of a new highly extended high-efficiency range Doherty power amplifier (DPA) for high peak to average power ratio (PAPR) communication signals were presented with a main and only a single auxiliary amplifier. In order to extend the output high-efficiency range, it employed non-equal cells as main and auxiliary amplifiers in the complex combining load (CCL) methodology. As a new method, a new design parameter ( $$\gamma$$ ) was added to the conventional complex combining load method. The effect of the new added design parameter on extension of output back-off (OBO) were analyzed and formulated. Also, to verify the proposed methodology, a DPA with 12 dB of OBO was designed, simulated and fabricated for WCDMA applications. Large signal continuous wave measurement results show the power gain of 11 dB with the drain efficiency of 53% at 12 dB of OBO. Two-tone test exhibits the third-order intermodulation distortion lower than − 34 dBc. Modulated wave simulations show over 51% of average drain efficiency and lower than − 31 dBc of adjacent channel leakage power ratio at output power level of 31.5 dBm.

A broadband high-efficiency Doherty power amplifier using symmetrical devices * * Project supported by the National Natural Science Foundation of China (No. 60123456), the Zhejiang Provincial Natural Science Foundation of China (No. LZ16F010001), and the Zhejiang Provincial Public Technology Research Project (No. 2016C31070).

This paper proposes a method for broadband and high-efficiency amplification of Doherty power amplifier (DPA) using symmetric devices. In order to achieve the perfect load modulation, the carrier amplifier output circuit total power length is designed to odd multiple of 90°, and the peak amplifier output total power length is designed to even multiple of 180°. The proposed method is demonstrated by designing a broadband high-efficiency DPA using identical 10-W packaged GaN HEMT devices. Measurement results show that over 51% drain efficiency is achieved at 6-dB back-off power, over the frequency band of 1.9–2.4 GHz.

Broadband high-efficiency Doherty power amplifier based on novel phase and impedance transform structure

Broadband high-efficiency Doherty power amplifier based on novel phase and impedance transform structure

A High Efficiency Doherty Power Amplifier for TV Band Applications

This paper presents a high efficiency Doherty power amplifier suitable for TV band applications. A class AB power amplifier is firstly implemented using a commercial GaN HEMT from Cree Incorporation, achieving a high power-added-efficiency of 77.78% and a 40.593 dBm output power with an associated gain of 21.65 dB. The Doherty amplifier has then been designed following the previous class AB scheme for the main amplifier and a class C scheme for the peak one. This amplifier attained a high power-added-efficiency of 81.94%, a 42.77 dBm output power, an associated gain of 21.32 dB, and an operating frequency bandwidth between 550 and 1000 MHz (58.06% fractional bandwidth) which made it suitable for TV band applications.

Doherty Power Amplifier with Dynamic Power Dividing Network for Enhanced Efficiency

In this paper, we present a high efficiency Doherty power amplifier (PA) employing dynamic power dividing network which automatically adjusts the input power division ratio in accordance with the level of input power to enhance efficiency. Doherty PA circuit parameters of each amplifier are determined by basic performance analysis according to the datasheet. Simulated circuits through Advanced Design System (ADS) exhibit an improvement of 4% at a 6 dB backoff point from its saturated output power (PSAT) than that of a conventional Doherty PA. Implemented Doherty PA using two Freescale MRF6S27015N laterally diffused metal oxide semiconductor (LDMOS) field-effect transistors (FETs) achieves excellent drain efficiency of 46.5% at a 6 dB backoff point from PSAT, which is 2% higher than conventional Doherty PA.

Inverted-load network for high-power Doherty amplifier

In this article, a high-power, high-efficiency inverted Doherty power amplifier (PA), having a more compact load network than that of the conventional Doherty amplifier, was designed and implemented for wide-band code-division multiple access (WCDMA) base-station applications. Its configuration and working principle are compared with the conventional Doherty amplifier. For experimental verification, we implemented an inverted Doherty amplifier, using a 190 W peak-envelope-power (PEP) laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors (FETs). Using a four-carrier down-link WCDMA signal, we achieved a high power-added efficiency (PAE) of 32% and an average output power level as high as 46.3 dBm at a given adjacent channel leakage ratio (ACLR) level of -30 dBc. This is a 9.5% improvement in efficiency and 1 dB improvement in output power under the same ACLR conditions from those of the balanced class-AB operation using the same devices.

Advanced design methods for a high efficiency Doherty power amplifier

AbstractIn this study, a special inverted Doherty topology and uneven power drive methods are proposed to optimize the efficiency and appropriate load modulation. The amplifier is optimized at large power back‐off. The power added efficiency and adjacent channel leakage ratio (ACLR) are 33.1% and −47 dBc, which improve by 3.2% and 5 dB, respectively, and its third‐order intermodulation distortion (IMD3) has 2 .5 dB improvement compared with conventional Doherty power amplifier. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1330–1333, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23375

A High Linearity and Efficiency Doherty Power Amplifier for Retrodirective Communication

This paper presents a Doherty power amplifier with advanced design methods for high efficiency and linearity applied to retrodirective communication system for high peak to average power ratio (PAR). A special inverted Doherty topology is proposed in order to optimize the average efficiency of Doherty amplifier. Also we develop Doherty power amplifier with uneven power drive which is provided more input power to the peak amplifier than carrier amplifier for full power operation and appropriate load modulation. These methods are applied to implement Doherty power amplifier using GaAs FET. The amplifier is optimized at large power back-off. The power added efficiency (PAE) and adjacent channel leakage ratio (ACLR) are 33.1% and −47 dBc, which improves about 3.2% and 5 dB respectively, its third-order intermodulation distortion (IMD3) has 2.5 dB improvement compared with conventional Doherty power amplifier.

마이크로파용 고효율 Doherty 전력증폭기 설계

In this paper, the high efficiency Doherty power amplifier has been designed and realized for microwave applications. The Doherty amplifier has been implemented using silicon MRF 281 LDMOS FET. The RF performances cf the Doherty power amplifier (a combination of a class AB carrier amplifier and a bias-tuned class C peaking amplifier) have been compared with those of a class AB amplifier alone. The realized Doherty power amplifier P1dB output power has 33dBm at 2.3GHz frequency. Also the Doherty power amplifier shows 11dB gain and -17.8dB input return loss at 2.3GHz to 2.4GHz. The designed Doherty amplifier has been improved the average PAE by 10% higher efficiency than a class AB amplifier alone. The Maximum PAE of designed Doherty power amplifier has been 39%.