Abstract
A design methodology of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$ </tex-math></inline-formula> -band high-efficiency Doherty power amplifier (DPA) with harmonic control is presented in this letter. The equivalent parasitic network (EPN) of the packaged device is constructed by a deembedding technique. The phase delay caused by the transistor parasitics is calculated using the scattering matrix of the EPN. Besides, the influence of the phase delay on DPA design is analyzed. To improve the efficiency at output back-off (OBO) power level, postmatching network (PMN) is used to control the second harmonic. A high-efficiency DPA working over 6.4–7.1 GHz is implemented, fabricated, and measured. The DPA delivers a saturation output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {sat}}$ </tex-math></inline-formula> ) of 39.6–41.6 dBm. Meanwhile, the drain efficiencies in the interested frequency band are 45.1%–53.2% and 34.5%–43.1% at the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {sat}}$ </tex-math></inline-formula> and 6-dB OBO power levels, respectively.
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