High Drain Efficiency Research Articles

On the improved RF performance of step field plate LDMOS transistor

This paper presents an analysis of the Step Field Plate Laterally Diffused Metal Oxide Semiconductor (SFP LDMOS) structure for improved high power and RF performance. The proposed structure is cost-effective, CMOS integrable, and has a high power figure of merit (FoM) due to its high off-state breakdown voltage (BVDS,off) and low specific on-resistance (Rsp). Significant improvement in frequency behavior is observed, as demonstrated by the flatter trans-conductance (gm), 12.5x lower gate-to-drain capacitance (Cgd), 2.5x lower gate-to-source capacitance (Cgs), and lower output conductance (gds). Single tone and double tone analyses are performed on an RF PA circuit implemented in TCAD. Results show ∼5 dBm higher output power (Pout), ∼6 dB higher power gain, and 46% higher drain efficiency (η), which are attributed to ∼1.9x lower drain-to-source capacitance (Cds) and ∼15 dBm lower magnitude of third-order intermodulation distortion due to lower third order derivative of drain current (ID). The paper also explains the device physics behind these observations.

Resistive‐reactive class‐X power amplifier with bandwidth beyond one octave

AbstractThis article presents a resistive‐reactive Class‐X power amplifier (PA) with bandwidth beyond one octave. By introducing resistive component into the second‐harmonic load of Class‐X power amplifier, the impedance design space is expanded. The basic theory of extended Class‐X PA is deduced, including impedance calculation, high‐efficiency design consideration and targeted impedance trace design. An impedance overlapping region between fundamental and second‐harmonic impedances with high drain efficiency is obtained, paving the way for bandwidth enhancement. For validation, the Class‐X and extended Class‐X theory are employed to design a broadband PA with bandwidth of 0.6–2.6 GHz (125%), drain efficiency of 57%–70%, and gain of 10.2–13.2 dB.

Coding Efficiency Enhancement Using Time Interleaved Level Splitting and Optimized Multi-Level Delta Sigma Modulation in Digital Transmitter

This paper proposes a novel scheme for energy-efficient transmitter design using optimized multi-level DSM (OML-DSM) along with time-interleaved level splitting technique. This scheme significantly improves the overall transmitter efficiency by providing high coding efficiency (CE) at the DSM stage and high drain efficiency (DE) at the amplification stage. The position of quantization level and quantization level selection window range is optimized in OML-DSM to achieve better CE compared to conventional multi-level DSM. These optimized multi-level signals are further split into bi-level signal streams using time-interleaved level splitting technique to improve the DE at the amplification stage. A 10 MHz LTE signal with 12 dB PAPR is used for simulation and measurement purposes. For hardware validation, 6-level OML-DSM is applied, which converts the 10 MHz LTE signal into six quantization levels and level splitter split these multi-levels into three bi-level signal streams with different magnitude and power levels. These bi-level signal streams are amplified using class-E SMPAs. The output of SMPAs is combined with Gysel unequal power combiner. Hardware results show that the CE and channel efficiency is improved by 18.7%, and 11.4%, respectively, compared to conventional 6-level DSM. The measured EVM is 2.2%, which shows good in-band performance.

High gain over an octave bandwidth class-F RF power amplifier design using 10W GaN HEM

The wireless communication industry grows faster each day. In terms of RF power amplifier (RFPA), the requirements on efficiency, linearity, bandwidth, output power and cost are getting more stringent. RFPA is considered as the most important component because of consuming large power in a base station. In this paper, a systematic approach is used to design a high flat gain class-F RFPA over an octave bandwidth. The simulation of a 1.5GHz class-F power amplifier mode demonstrates a high drain efficiency while accomplishing a high flat gain over a wide bandwidth. To identify the optimum impedance for the output matching and input matching network, the load-pull and source-pull are performed. The simulation results show that the RFPA can deliver a drain efficiency of 68.37 % at the output power of 40.79 dBm with power added efficiency of 66.94 %. The designed PA achieved a high gain between 13 dB to 17 dB from 0.5 GHz to 2.0 GHz of a frequency band. The matching circuits are realized on an FR-4 substrate to keep the cost as low as possible. A 10W GaN HEMT CGH40010 transistor from Cree has been used for this RFPA design.

Analysis and Design of Outphasing Transmitter Using Class-E Power Amplifiers With Shunt Capacitances and Shunt Filters

In this paper, a novel outphasing power amplifier (PA) based on class-E amplifiers with shunt capacitances and shunt filters is proposed. The new design provides high drain efficiency for both peak and back-off power levels. A mathematical model for the class-E power amplifier with shunt capacitance and shunt filter is presented. The proposed model enables derivation of load circuit parameters that provide optimum drain efficiency for the peak and back-off power levels using closed form mathematical expressions. Based on this model, an outphasing power amplifier is designed and subsequently implemented using microstrip transmission lines and a GaN HEMT devices. The fabricated power amplifier prototype is optimized for 2.14 GHz and provides drain efficiency of over 60% for back-off power levels up to 8.5 dB. The amplifier demonstrates a 44.3% drain efficiency for 64QAM OFDM modulated signal with 20 MHz bandwidth. Adjacent channel leakage ratio (ACLR) of −39.5 dB and error vector magnitude (EVM) of 0.9 % were achieved after the application of a memory polynomial linearization algorithm.

Investigation of Input–Output Waveform Engineered Continuous Inverse Class F Power Amplifiers

An in-depth analysis of the continuous inverse Class F power amplifier (PA) accounting for nonlinear input and output active device properties is presented. The analyses show possible ways of exploiting input nonlinearity to improve and maintain PA performance in a broadband operation and propose a flexible source second-harmonic design space which reduces the input matching network (MN) design complexities. Such exploitation of input nonlinearity can also alleviate performance degradation due to dynamic knee behavior of a practical field-effect transistor (FET) in continuous inverse Class F PA operation. The analyses are validated with vector load–pull (VLP) measurements and utilized to implement a broadband PA design. High-drain efficiency (DE) over 75% and output power more than 38 dBm are achieved over 0.8–1.4 GHz at constant 3-dB gain compression.

Striving for Efficiency: A 475-kHz High-Efficiency Two-Stage Class-E Power Amplifier

This article presents the design and validation for the high-efficiency class-E power amplifier (PA) that won first place in the high-efficiency PA for 475 kHz Student Design Competition held during the 2018 IEEE Microwave Theory and Techniques Society International Microwave Symposium (IMS 2018) in Philadelphia, Pennsylvania. Participants were required to implement and evaluate their own PAs. The team that achieved the highest drain efficiency while satisfying the conditions of the competition rules was the winner.

High Drain Efficiency and High Linear Two Inverted Way Doherty Amplifier with High Power for CDMA Signal

A novel high drain efficiency two inverted Doherty amplifier is presented, A carrier amplifier and a peak amplifier are set to asymmetrical drain voltages to extend the power range where a high efficiency of the amplifier is maintained, matching circuits of the carrier amplifier and peak amplifier in the two inverted Doherty amplifier are designed for each drain voltage so that the efficiency and signal linearity of the amplifier at a 6.8dB back-off point from its’ saturated output power (Psat) become higher than those of a conventional amplifier. A Doherty amplifier containing laterally-diffused metal-oxide semiconductor (LDMOS) field-effect transistors (FETs) achieves an adjacent channel leakage power ratio (ACLR) of -30.8dBc and a drain efficiency of 50% at an output power of 49.3dBm.This is the highest drain efficiency of a Doherty amplifier use LDMOS for a WCDMA signal to the best of the authors’ knowledge.

Highly Efficient Fully Integrated GaN-HEMT Doherty Power Amplifier Based on Compact Load Network

This paper presents a fully integrated gallium-nitride high-electron-mobility transistor (GaN-HEMT) Doherty power amplifier (DPA) based on a compact load network for small-cell applications. The gate width of the transistor is optimized to have a load impedance of $100~\boldsymbol{\Omega }$ with a shunt inductor that can compensate for the output capacitor using a parallel resonance. A quarter-wave transmission line (TL) with a characteristic impedance of $100~\boldsymbol{\Omega }$ is realized using a high-pass ${\pi }$ -type lumped network for the carrier amplifier. The on-chip input network, including a power splitter, a quarter-wave TL, and matching networks for the carrier and peaking amplifiers, is designed using lumped components. The circuits are simplified by merging the multiple shunt components at a node into an inductor or a capacitor. As a result, the load network has only two shunt inductors. To verify the proposed circuits, a 2.6-GHz DPA integrated circuit (IC) was designed and implemented using a 0.4- ${\mu }\text{m}$ GaN-HEMT process. The implemented IC, which was mounted on a quad-flat no-lead package, exhibited a high drain efficiency of 54.4% at an average output power of 37.6 dBm with an adjacent channel leakage power ratio of −27.0 dBc using a downlink long-term evolution signal having a channel bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB.

Design of inverse Class‐F power amplifier based on dual transmission line with 87.4% drain efficiency

AbstractIn this paper, an inverse Class‐F power amplifier (PA) based on dual transmission line (DTL) is presented. The output matching network (OMN) with DTL has a simple and compact circuit topology compared with other harmonic‐tuned OMNs with open/short shunt stubs and provides up to 6th harmonic suppression. In addition, the DTL structure is equivalent to a quarter wavelength transformer for fundamental matching. A GaN HEMT is adopted to achieve high output power and high drain efficiency in the proposed inverse Class‐F PA. Finally, a 2.4 GHz inverse Class‐F PA is designed and fabricated. The experimental results show the highest drain efficiency of 87.4% in the operating frequency with the corresponding output power of 44.5 dBm, and adjacent channel power ratio (ACPR) of −50.8/‐51.6 dBc with digital predistortion technique (DPD) at 2.4 GHz.

Design of Multioctave Bandwidth Power Amplifier Based on Resistive Second-Harmonic Impedance Continuous Class-F

In this letter, a generic method is presented for multioctave power amplifier (PA) based on extended version of the continuous class-F. The theory allows resistive second-harmonic impedance and sacrifices part of efficiency to get a bandwidth over one octave. A high-voltage GaN HEMT is adopted to achieve high output power and drain efficiency. Finally, a 0.2–2.5 GHz miniature multioctave PA is designed and fabricated. Experimental results show the drain efficiency of 55.5%–70.3% and the output power of 43.7–46.9 dBm across 0.2–2.5 GHz (170%). The compact size of the proposed PA can also be observed with only 2.6 cm $\times5.5$ cm, which is greatly reduced compared with other PAs with similar performances.

Compact Load Network for GaN-HEMT Doherty Power Amplifier IC Using Left-Handed and Right-Handed Transmission Lines

This letter presents a compact load network for Doherty power amplifier (DPA) integrated circuits (ICs) using ${\pi }$ -type left-handed (LH) and right-handed (RH) transmission lines (TLs) based on lumped components. The quarter-wave impedance transformers based on the LH TLs and a compensation method for the internal shunt capacitance using a shunt inductor were adopted for the impedance matching networks. The ${\pi }$ -type LH and RH TLs for the matching networks and a combining network can be further simplified by merging adjacent shunt components. In order to verify the proposed load network, a 2.6-GHz DPA IC was designed and fabricated using a 0.4- ${\mu }\text{m}$ gallium nitride high-electron-mobility transistor process for small-cell base stations. The overall size of the chip is $1.7\times 1.8$ mm2 and the chip was mounted on a quad flat no-leads package. For a long term evolution signal with a signal bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB, a high drain efficiency of 52.2% was obtained at an average output power of 34.0 dBm.

A Highly Efficient Power Amplifier at 5.8 GHz Using Independent Harmonic Control

An optimal design of a highly efficient power amplifier (PA) is described using independent fundamental and second harmonic impedance control technique. In fabrication of a power amplifier, a tuning method is indispensable because the simulation models of the device and capacitor have some difference with the actual value. To achieve a high drain efficiency, the fundamental and harmonic impedances need to be accurately optimized. However, as the operating frequency is increased, the matching circuit becomes sensitive and it is difficult to realize the accurate optimum matching. To solve the problem, the matching circuit of the PA adopts the independent harmonic control circuit using the characteristic of a quarter-wavelength microstrip line. A power amplifier with the concept is designed and implemented using a Cree GaN HEMT CGH40035 at 5.8 GHz. The peak output power, drain efficiency and gain are 47.2 dBm, 70.2%, and 10.2 dB.

Prospects and Limitations of Stacked-FET Approaches for Enhanced Output Power in Voltage-Controlled Oscillators

This paper reports on the emerging potential of a stacked field-effect transistor (FET) approach with respect to maximum achievable RF output power with special remarks on high electron-mobility transistor (HEMT) based series feedback oscillator monolithic microwave integrated circuits (MMICs). A stacked-FET oscillator can provide benefit in several ways—in the form of an improved RF output power, a high drain efficiency, or a stabilized oscillation behavior, even for changing load impedances. The limitation of the maximum number of transistors is analyzed with reference to the maximum achievable output power of stacked devices. This is done by describing the compromise between an increased voltage swing and a decreased RF output current. The output current is decreased since the current gain of a common gate device is smaller than unity. Based on the proposed theory a W-band stacked-FET voltage-controlled oscillator MMIC with an output power of 15 dBm and a drain efficiency of 23.3% was realized. The MMIC is based on the Fraunhofer IAF 50-nm gate-length metamorphic HEMT process. For an advanced evaluation of the power capability and the optimum target load of the utilized technology, an active W-band on-wafer load–pull system was implemented.

Design of Ku‐band GaN HEMT power amplifier based on multi‐bias statistical model

AbstractA design method for microwave GaN high‐electron mobility transistor (HEMT) power amplifier based on equivalent circuit parameters multi‐bias statistical models is presented. The statistical modeling method includes principal component analysis, factor analysis, and multiple regressions modeling techniques. The statistical model is validated by comparing original and Monte Carlo‐simulated means, standard deviations, correlation matrix, and S‐parameters. A Ku‐band GaN HEMT power amplifier is designed with high drain efficiency by using the established statistical model for demonstration purpose. The simulated results are statistically indistinguishable from the measured results. This method is suitable for GaN HEMT power amplifier design and yield analysis. Copyright © 2015 John Wiley & Sons, Ltd.

A 40–67 GHz Power Amplifier With 13 dBm ${\rm P}_{\rm SAT}$ and 16% PAE in 28 nm CMOS LP

Pushed by the availability of large fractional bandwidths, many well-established applications are focusing mm-wave spectrum for product deployment. Generation of broadband power at mm-waves is challenging because a key target such as the efficiency trades with the gain-bandwidth (GBW) product. The major limit is the capacitive parasitics at the interstage between driver and power devices. The latter are designed with a large form factor so as to deliver the desired output power and are commonly biased in class-AB to achieve high drain efficiency, penalizing GBW. In this paper, a design methodology for interstage and output matching networks targeting large fractional bandwidth and high efficiency is proposed. Leveraging inductively coupled resonators, we apply Norton transformations for impedance scaling. In both networks, topological transformations are employed to include a transformer, achieve the desired load impedance and minimize the number of components. A two-stage differential PA with neutralized common source stages has been realized in 28 nm CMOS using low-power devices. The PA delivers 13 dBm saturated output power over the 40–67 GHz bandwidth with a peak power-added efficiency of 16% without power combining. To the best of author's knowledge, the presented PA shows state-of-the-art performances with the largest fractional bandwidth among bulk CMOS mm-wave PAs reported so far.

DESIGN OF ASYMMETRICAL DOHERTY POWER AMPLIFIER WITH REDUCED MEMORY EFFECTS AND ENHANCED BACK-OFF EFFICIENCY

This paper presents the design of an asymmetrical Doherty power amplifier (DPA) with improved linearity and efficiency performance. Resonator-type drain bias networks, providing high impedances at the carrier frequency and low impedances with small variation at the envelope frequency, are introduced to reduce the DPA's memory effects when transmitting wideband signals. The general criteria for DPA design are summarized, and the approach to obtain optimum fundamental and harmonic impedances is proposed to achieve back-off efficiency enhancement. For experimental validation, the asymmetrical DPA is designed and implemented using two identical GaN HEMTs. Measured with continuous wave (CW), the proposed DPA delivers a saturation power greater than 49.3 dBm from 3400 to 3600 MHz, along with high drain efficiency of over 62% and 48% at peak and 8-dB back-off power, respectively. Driven with 100-MHz LTE-advanced signals, the adjacent channel leakage ratio (ACLR) asymmetry of the DPA at 20-MHz offset is lower than 1-dB. After digital predistortion (DPD) linearization, the proposed DPA achieves an ACLR of better than �48 dBc at an average output power about 41 dBm and the drain efficiency over 45% across the frequency band.

A Wideband Doherty Power Amplifier With 100 MHz Instantaneous Bandwidth for LTE-Advanced Applications

In this letter, a 698-862 MHz wideband Doherty power amplifier (DPA) with 100 MHz instantaneous bandwidth is presented. The electrical memory effect of the wideband DPA is reduced by the LC resonant circuits employed in the drain bias networks. The influence of the integrated Doherty combiner is compensated by the broadband output matching networks, which were designed by applying the simplified real frequency technique. Driven with 100 MHz LTE-advanced signals, the adjacent channel leakage ratio (ACLR) and ACLR asymmetry of the proposed DPA at 20 MHz offset are improved by about 4 dB and 3 dB respectively, compared to the wideband DPA with conventional bias networks. After digital predistortion (DPD) linearization, the proposed DPA shows an ACLR of lower than -48 dBc at an average output power of 42.5 dBm, and high drain efficiency of over 42% across the operating frequency range.

A 2.45-GHz $+$20-dBm Fast Switching Class-E Power Amplifier With 43% PAE and a 18-dB-Wide Power Range in 0.18-$\mu \hbox{m}$ CMOS

In this brief, the losses in Class-E power amplifiers (PAs) with finite dc-feed inductance are analyzed. This analysis results in practical analytical expressions, which significantly simplify the design and optimization of Class-E PAs. To demonstrate their applicability, the design of a state-of-the-art 2.45-GHz differential cascode Class-E PA in 0.18- CMOS with on-chip dc-feed inductor is presented. By the proposed combination of a dynamic supply voltage and a dynamic cascode bias voltage, high drain efficiency is achieved over a wide power control range, covering from 2.2 up to 20 dBm. At 20 dBm, a power-added efficiency as high as 43.6% was measured. Additionally, fast envelope switching is obtained by adding a single switch to the common-gate nodes of both the Class-E stage and the second driver stage. Measurements show a rise time of merely 2.5 ns and a 73-dB isolation between the on- and off-states. These figures enable ranging applications with submeter accuracy.

RF-MEMS based tri-band GaN power amplifier

An RF-MEMs based tri-band GaN power amplifier with state-of-the-art performance is presented. The active device is a low-cost GaN-on-Si transistor with a plastic package. A dedicated broadband output matching network is designed to provide the desired waveform at the device intrinsic level. The frequency reconfigurability is implemented with one RF-MEMS at the input stage. Measured results show a 45, 28 and 46% power added efficiency (PAE) for an output power of 5.6, 3.0 and 4.5 W at 1.4, 2.5 and 3.6 GHz, respectively. Furthermore, the power amplifier exhibits a high drain efficiency of more than 46% across 1.3–1.4 and 3.4–3.7 GHz whilst delivering an output power of more than 4.3 W.