Highly Efficient Fully Integrated GaN-HEMT Doherty Power Amplifier Based on Compact Load Network

Abstract

This paper presents a fully integrated gallium-nitride high-electron-mobility transistor (GaN-HEMT) Doherty power amplifier (DPA) based on a compact load network for small-cell applications. The gate width of the transistor is optimized to have a load impedance of $100~\boldsymbol{\Omega }$ with a shunt inductor that can compensate for the output capacitor using a parallel resonance. A quarter-wave transmission line (TL) with a characteristic impedance of $100~\boldsymbol{\Omega }$ is realized using a high-pass ${\pi }$ -type lumped network for the carrier amplifier. The on-chip input network, including a power splitter, a quarter-wave TL, and matching networks for the carrier and peaking amplifiers, is designed using lumped components. The circuits are simplified by merging the multiple shunt components at a node into an inductor or a capacitor. As a result, the load network has only two shunt inductors. To verify the proposed circuits, a 2.6-GHz DPA integrated circuit (IC) was designed and implemented using a 0.4- ${\mu }\text{m}$ GaN-HEMT process. The implemented IC, which was mounted on a quad-flat no-lead package, exhibited a high drain efficiency of 54.4% at an average output power of 37.6 dBm with an adjacent channel leakage power ratio of −27.0 dBc using a downlink long-term evolution signal having a channel bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB.