High-density Integrated Circuit Research Articles

Three-dimensional integrated metal-oxide transistors

AbstractThe monolithic three-dimensional vertical integration of thin-film transistor (TFT) technologies could be used to create high-density, energy-efficient and low-cost integrated circuits. However, the development of scalable processes for integrating three-dimensional TFT devices is challenging. Here, we report the monolithic three-dimensional integration of indium oxide (In2O3) TFTs on a silicon/silicon dioxide (Si/SiO2) substrate at room temperature. We use an approach that is compatible with complementary metal–oxide–semiconductor (CMOS) processes to stack ten n-channel In2O3 TFTs. Different architectures—including bottom-, top- and dual-gate TFTs—can be fabricated at different layers in the stack. Our dual-gate devices exhibit enhanced electrical performance with a maximum field-effect mobility of 15 cm2 V−1 s−1, a subthreshold swing of 0.4 V dec−1 and a current on/off ratio of 108. By monolithically integrating dual-gate In2O3 TFTs at different locations in the stack, we created unipolar invertor circuits with a signal gain of around 50 and wide noise margins. The dual-gate devices also allow fine-tuning of the invertors to achieve symmetric voltage-transfer characteristics and optimal noise margins.

Frequency doubler utilizing hetero gate dielectric tunnel field-effect transistor

With the rapid advancements in wireless communication and high-density integrated circuits, the demand for high-frequency sources has become paramount for transmitting vast amounts of information. Modern communication systems often utilize low-frequency sources at the transmitting end, converting them into high-frequency carriers through Intermediate Frequency (IF) for transmission to the receiving end. However, challenges arise in stabilizing high-frequency Voltage Controlled Oscillators (VCOs), leading to the necessity of Frequency Multipliers (FMs) in high-frequency circuits. While existing FMs face issues like harmonic distortion due to internal nonlinear devices, this paper proposes a single-device Frequency Doubler (FD) operation using Hetero-Gate Tunnel Field Effect Transistor (HG-TFET) with ambipolar characteristics. HG-TFET integrates high-κ (HK) materials and an HG structure in the gate dielectric, achieving independent control of tunneling distances and synchronous operation of source-to-channel and channel-to-drain tunneling currents (I SC and I CD) to facilitate FD operation. The paper presents the HG-TFET structure, process flow, and simulation models, followed by an exploration of its operating mechanism and characteristics. The FD circuit configuration, operational principles, and conditions for normal operation are detailed, emphasizing the importance of aligning I SC and I CD. The impact of adjusting HK lengths on I SC and I CD is analyzed, demonstrating the ability to independently control these currents through HG-TFET. Simulation results for FD operation under varying HK lengths (1–10 nm) validate the proposed approach. Additionally, the paper investigates the influence of dielectric constant (10–32) and gate dielectric thickness (2–5 nm) on FD performance, highlighting the potential for further optimization. In conclusion, this study establishes a foundation for normal FD operation through the symmetrical control of ambipolar and on currents using HG-TFET. The proposed structure and techniques open avenues for improving the efficiency and reliability of frequency-doubling applications in high-frequency circuits.

Research on intermittent fault of bond wire under thermal and vibration shock based on simulation and experiments

As equipment usage environments become increasingly complex and harsh, the reliability of chips as the core of high-density integrated circuits becomes increasingly important. Bond wires, as weak links, are the focus of reliability research. Traditional research has focused on permanent failures, while intermittent failures have received little attention due to their unpredictable nature, but their existence cannot be ignored. This article simulates temperature shock and vibration environments on bond wires, demonstrating that the dangerous area of bond wires is located at the junction of the gold wire and the chip solder pad. It also explains that intermittent failures are caused by the degradation or potential damage of bond wires that are further damaged when subjected to environmental shocks, with the effective contact area of the damaged area changing with the shock and the resistance changing significantly. Based on the theory of contact resistance, relevant models were constructed for simulation, and the effect of micro-protrusion depth on contact resistance was studied. The article then designed and constructed an experimental circuit to carry out intermittent failure verification tests and studied the characteristics of intermittent failure currents. This research provides theoretical and technical support for the study of intermittent failures in high-density integrated circuits.

Full two-dimensional ambipolar CFET-like architecture for switchable logic circuits

As the scaling of integrated circuits based on silicon semiconductors becomes increasingly challenging due to the minimum feature size being close to the physical limit, the urgent demand for alternative strategies has fuelled the rapid growth of techniques and material innovations. Here, we report on the fabrication of vertically stacked ambipolar complementary field-effect transistor that is fully composed of two-dimensional materials of WSe2/h-BN/graphene/h-BN/WSe2 heterostructures. The ambipolar feature of the top and bottom WSe2 FET enables a switchable inverter behavior with a favorable voltage gain of up to 75, which can work in both the first and third quadrants. Based on the switchable characteristics, a large voltage swing circuit for single photon avalanche detectors is proposed without any bulky negative-voltage components. This work could open a new pathway for future two-dimensional electronics and ultimate monolithic 3D high-density integration circuits.

The Trend of 2D Transistors toward Integrated Circuits: Scaling Down and New Mechanisms.

2D transition metal chalcogenide (TMDC) materials, such as MoS2 , have recently attracted considerable research interest in the context of their use in ultrascaled devices owing to their excellent electronic properties. Microprocessors and neural network circuits based on MoS2 have been developed at a large scale but still do not have an advantage over silicon in terms of their integrated density. In this study, the current structures, contact engineering, and doping methods for 2D TMDC materials for the scaling-down process and performance optimization are reviewed. Devices are introduced according to a new mechanism to provide the comprehensive prospects for the use of MoS2 beyond the traditional complementary-metal-oxide semiconductor in order to summarize obstacles to the goal of developing high-density and low-power integrated circuits (ICs). Finally, prospects for the use of MoS2 in large-scale ICs from the perspectives of the material, system performance, and application to nonlogic functionalities such as sensor circuits and analogous circuits, are briefly analyzed. The latter issue is along the direction of "more than Moore" research.

Crosstalk suppression for high-density traveling-wave MZM array based on static and dynamic combined analysis and circuit-level designs.

Electrical crosstalk severely degrades the performance of Mach-Zehnder modulator (MZM) array. However, conventional crosstalk suppression techniques incur losses of large amounts of chip area for signal isolation, which becomes a bottleneck of high-density electronic-photonic integrated circuit. In this paper, the electrical crosstalk of Traveling-Wave MZM array is originally analyzed with static and dynamic combined crosstalk coefficients. Circuit-level suppression techniques of differential dual-drive electrode schemes with tightly coupled electrode pairs and a virtual ground structure with full-matching termination circuit are investigated for noise-removing effects. Simulation results show that the dynamic electrical crosstalk coefficient between two adjacent modulators is reduced to below 1.5%, which is five times lower than the baseline. The electro-optical link measurements show that the BER is significantly reduced from 1E-3 to 1E-12 for multi-channel operation, which confirms the effectiveness of the crosstalk suppression techniques.

Sensitivity Enhancement of Group Refractive Index Biosensor through Ring-Down Interferograms of Microring Resonator.

In recent years, silicon-on-insulator substrates have been utilized for high-speed and low-power electronic components. Because of the high refractive index contrast of the silicon wire, its photonic device footprint can be significantly reduced. Moreover, the silicon photonic process is compatible with a complementary metal-oxide-semiconductor fabrication, which will benefit the high-density optoelectronic integrated circuits development. Researchers have recently proposed using the microring resonator (MRR) for label-free biosensing applications. The high-quality factor caused by the substantial electric field enhancement within the ring makes the MRR a good candidate for biomolecule detection under low analyte concentration conditions. This paper proposes an MRR chip to be a biosensor on the silicon platform through the relative displacement between the spatial ring-down interferograms at various cladding layers. The higher-order ring-down of the spatial interference wave packet will enhance the biosensing sensitivity after optimizing the coupling, MRR length, and the optical source bandwidth at the fixed optical waveguide loss. Finally, a typical sensitivity of 642,000 nm per refractive index unit is demonstrated under 0.1 μW minimum optical power detection for an MRR with a 100 μm radius. Higher sensitivity can be executed by a narrow bandwidth and lower silicon wire propagation loss.

Nanocomposites for future electronics device Packaging: A fundamental study of interfacial connecting mechanisms and optimal conditions of silane coupling agents for Polydopamine-Graphene fillers in epoxy polymers

With the ultra-fast development of high-performance semiconductor devices through the increase of power and on-chip integration density, it is essential to maximize heat transfer efficiency and explore new nanomaterials for applications in thermal interface materials (TIMs). Graphene-based epoxy nanocomposites are becoming one of the most promising candidates for the next generation of highly efficient, lightweight TIMs due to the unique properties of graphene – extraordinarily high thermal conductivities and large surface areas. However, they can have poor interfacial interactions with polymers owing to the lack of functional groups on the surface of graphene, leading to phonon scattering within the contact interfaces. In this work, graphene nanosheets are fabricated by a large-scale and low-cost liquid exfoliation method. Through fundamental understandings of interfacial connecting mechanisms and intelligent modifications of graphene with polydopamine (PDA) and silane coupling agents, optimized reaction conditions between silane coupling agents and PDA-graphene serve as the main contributor to the high thermal conductivity of the epoxy nanocomposites with low viscosity and effective filler dispersion. The graphene epoxy nanocomposites thus obtained have an out-of-plane thermal conductivity of 0.73 W/mK at 5 wt% loading, corresponding to a 400% improvement in thermal conductivity as compared to that of neat epoxy. In addition, the nanocomposites also have a lower coefficient of thermal expansion (CTE), higher thermal stability, lower moisture adsorption, and effective electrical insulation. From performance tests on the TIMs, they present better cooling capabilities and heat dissipation as corroborated through both experimentation and simulation, supporting the idea that our findings have potential to be applied in the next generation of TIMs for high-power and high-density integrated circuits (ICs) as well as in advanced packaging.

Ultrahigh-rate and high-frequency MXene micro-supercapacitors for kHz AC line-filtering

Harnessing energy from the environment promotes the rapid development of micro-power generators and relevant power management modules of alternating current (AC) line-filtering to obtain a stabilized direct current (DC) output for storage and use. Micro-supercapacitors (MSCs) with miniaturized volume and high-frequency response are regarded as a critical component in filtering circuits for microscale power conversion. Here, we reported the fabrication of the wafer-sized planar MSCs (M-MSCs) based on 2D Ti3C2Tx MXene using a photolithography technique. The M-MSCs exhibited an areal capacitance of 153 μF cm−2 and a frequency characteristic (f0) of 5.6 kHz in aqueous electrolyte. Moreover, by employing suitable ionic liquid as electrolyte, the voltage window was expanded to 2 V and the f0 could be pushed to 6.6 kHz relying on the electrical double-layer mechanism and lower adsorption energy while maintaining quasi-rectangular cyclic voltammogram curves at 5000 V s−1. Furthermore, the integrated MSCs pack was constructed and exhibited excellent rectifying ability by filtering various high-frequency 5000 Hz AC signals with different waveforms into stable DC outputs. Such ultrahigh-rate and high-voltage M-MSCs module for kHz AC line-filtering would be potentially integrated with customizable electronics to realize on-chip rectifiers in high-density integrated circuit.

Low-threshold and narrow-linewidth perovskite microlasers pumped by a localized waveguide source

Abstract For the widely used vertically pumped (VP) method with a free-space beam, very little pump power is absorbed by the gain materials in microlasers because of the large spatial mismatch of areas between laser modes and free-space pump beams together with small thicknesses of gain materials, resulting in a high pump power threshold. Here, an in-plane-waveguide-pump (IPWP) method with a localized waveguide source is proposed to reduce pump power threshold of perovskite microlasers. Owing to reduced spatial mismatch of areas between laser modes and localized waveguide sources as well as increased absorption distances, the pump power threshold of the IPWP method is decreased to approximately 6% that of the VP method. Moreover, under the same multiple of the pump power threshold, the laser linewidth in the IPWP method is narrowed to approximately 70% that in the VP method. By using the IPWP method, selective pumping two adjacent (separation 2 or 3 μm) parallel-located perovskite microlasers is experimentally demonstrated, and no crosstalk is observed. This IPWP method may have applications in low-energy and high-density microlasers and photonic integrated circuits.

Ultra-compact electro-optic modulator based on alternative plasmonic material.

We propose an ultra-compact electro-optic microring modulator based on a hybrid plasmonic waveguide. In comparison to previously proposed structures, the present structure utilizes aluminum-doped zinc oxide (AZO), rather than noble metals, for plasmon excitation. AZO can be used to simultaneously tune both the real and imaginary parts of the dielectric constant by changing the carrier concentration. The modulation depth and insertion loss of the microring modulator are 18.70 and 2.76 dB. The proposed modulator has a high modulation speed because its capacitance is 0.22 fF. This device could be used in high-density integrated optical circuits.

A novel solder joint diagnosis algorithm using differential geometry approach in high-density flexible integrated circuit substrates

To provide a system with high-density solder joint 3D information acquisition and improve the comprehensive performance of automatic optical inspection systems, a novel diagnosis system for solder joints of high-density flexible integrated circuit substrates is proposed in this paper. The differential geometry principle is introduced to analyze the appearance identity of solder joints, and the diagnosis is handled as a pattern-recognition problem with the Frenet frame-matching approach. First, a high-precision 3D information-acquisition system constituted of two CCD digital cameras, each with a microscope and a three-color LED illumination, is developed. Second, a discrete estimation scheme based on the differential geometry theory is proposed to achieve curvature measurement, and then the shape of the solder joints is characterized by the crest line representation method. Finally, the classification strategy is to establish different models of solder joint types and make a decision based on a set of the predefined diagnosis rules. By inspecting various types of solder joints and comparing with other typical algorithms, the performance of the proposed system is evaluated. The experiment results indicate that the proposed algorithm has advantages of fast inspection speed, low misjudgment rate, which is reduced to 2.2%, and detailed classification.

The Design and Research of a New Hybrid Surface Plasmonic Waveguide Nanolaser.

Using the hybrid plasmonic waveguide (HPW) principle as a basis, a new planar symmetric Ag-dielectric-SiO2 hybrid waveguide structure is designed and applied to nanolasers. First, the effects on the electric field distribution and the characteristic parameters of the waveguide structure of changes in the material, the nanometer radius, and the dielectric layer thickness were studied in detail using the finite element method with COMSOL Multiphysics software. The effects of two different dielectric materials on the HPW were studied. It was found that the waveguide performance could be improved effectively and the mode propagation loss was reduced when graphene was used as the dielectric, with the minimum effective propagation loss reaching 0.025. Second, the gain threshold and the quality factor of a nanolaser based on the proposed hybrid waveguide structure were analyzed. The results showed that the nanolaser has a lasing threshold of 1.76 μm−1 and a quality factor of 109 when using the graphene dielectric. A low-loss, low-threshold laser was realized, and the mode field was constrained by deep sub-wavelength light confinement. This structure has broad future application prospects in the integrated optics field and provides ideas for the development of subminiature photonic devices and high-density integrated circuits.

An 8-Bit Full-Adder Implementation Using Single Electron Tunneling (SET) Technology (Dept.E)

Single Electron Tunneling (SET) devices have come to be considered as promising candidates for future ultra-low power and high-density integrated circuits. Their potential for ultra-low power is related to that the operation is based on only a few electrons. The term Single Electron Tunneling (SET) technology has been selected for devices sensitive to the manipulation of a single electron even if the device itself requires in fact few electrons. Besides, SET provides a simple and elegant solution for implementing threshold Logic Gates (TLGs). This paper presents a SET TLG one-bit full-adder implemented in SET technology. The paper then introduces the design and implementation of an 8-bit SET TLG full-adder and presents its SIMON 2 simulation results.

Efficient light coupling between an ultra-low loss lithium niobate waveguide and an adiabatically tapered single mode optical fiber

A lithium niobate on an insulator ridge waveguide allows constructing high-density photonic integrated circuits thanks to its small bending radius offered by the high index contrast. Meanwhile, the significant mode-field mismatch between an optical fiber and the single-mode lithium niobate waveguide leads to low coupling efficiencies. Here, we demonstrate, both numerically and experimentally, that the problem can be solved with a tapered single mode fiber of an optimized mode field profile. Numerical simulation shows that the minimum coupling losses for the TE and TM mode are 0.32 dB and 0.86 dB, respectively. Experimentally, though without anti-reflection coating, the measured coupling losses for TE and TM mode are 1.32 dB and 1.88 dB, respectively. Our technique paves a way for a broad range of on-chip lithium niobate applications.

Improvement on Fully Filled Through Silicon Vias by Optimized Sputtering and Electroplating Conditions.

The high reliability of electroplating through silicon vias (TSVs) is an attractive hotspot in the application of high-density integrated circuit packaging. In this paper, improvements for fully filled TSVs by optimizing sputtering and electroplating conditions were introduced. Particular attention was paid to the samples with different seed layer structures. These samples were fabricated by different sputtering and treatment approaches, and accompanied with various electroplating profile adjustments. The images were observed and characterized by X-ray equipment and a scanning electron microscope (SEM). The results show that optimized sputtering and electroplating conditions can help improve the quality of TSVs, which could be interpreted as the interface effect of the TSV structure.

An novel image de-noising model based on gradient and adaptive curvature features and its application

In this paper, an image de-noising model with gradient and adaptive curvature features is proposed for the visual inspection of the appearance defects of high-density flexible integrated circuit package substrates with strict line-width and line distance. Firstly, the model proposed in this paper adaptively adjusts the weight of the level set curvature feature and the gradient feature of the image, and uses more abundant first-order differential and second-order differential information of the image as the detection factor for image de-noising. Secondly, theoretical analysis shows that the diffusion intensity of the model in the flat region is larger than that of the classical model, and the de-noising effect is better. Furthermore, at the corners and peaks of the image, the proposed model can suppress the reduction of the gray value and preserve more detailed information of the image and edges. Finally, the experimental analysis shows that the proposed model has the best de-noising effect compared with other models. The method proposed in this paper can effectively remove the noise of the image of the high-density flexible integrated circuit package substrate, and at the same time retain more original details and edge information of the image which has practical significance.

Plasmonic band-stop filters based on tooth structure

In this paper, the plasmonic band-stop filter with unilateral multi-tooth structure and the causes of Fano resonance are studied theoretically and numerically. Fine-tuning of the bandwidth and center wavelength can be achieved by varying the spacing and tooth depth between the tooth cavities. This phenomenon can be attributed to the interference superposition of reflected and transmitted waves from each tooth cavity. When the spacing between the tooth cavities changes, the position of the formant in the transmission spectrum changes as the resonant wavelength of the cavity changes. In the case where only the depth of the tooth is changed, the length of the red shift of the center wavelength of the band stop is almost twice as large as the depth of the tooth. The finite difference time domain method is used to simulate and calculate the coupling of surface plasmon waves of different structures in this paper. The plasmonic waveguide band-stop filters we propose here may have meaningful applications in ultra-fine spectral analysis and high-density nanoplasma integration circuits.

Growth and Fabrication of High‐Quality Single Nanowire Devices with Radial p‐i‐n Junctions

Nanowires (NWs) with radial p-i-n junction have advantages, such as large junction area and small influence from the surface states, which can lead to highly efficient material use and good device quantum efficiency. However, it is difficult to make high-quality core-shell NW devices, especially single NW devices. Here, the key factors during the growth and fabrication process that influence the quality of single core-shell p-i-n NW devices are studied using GaAs(P) NW photovoltaics as an example. By p-doping and annealing, good ohmic contact is achieved on NWs with a diameter as small as 50-60 nm. Single NW photovoltaics are subsequently developed and a record fill factor of 80.5% is shown. These results bring valuable information for making single NW devices, which can further benefit the development of high-density integration circuits.

A fast oxidation region detection algorithm based on differential geometry approach for high-density flexible integrated circuit packaging substrates

Vision inspection has been widely used in the field of defect measurement as a noncontact, nondestructive measurement technique. Conventional visual defect detection methods rely heavily on standard templates and image features, but the standard templates are either difficult to obtain or do not exist in many application fields, especially in flexible integrated circuit (IC) substrate defect detection at a microscopic level. To solve the above problems, a rapid online oxidation defect detection algorithm for micron-level flexible IC substrate oxidation defects, based on the differential geometric approach, is proposed in this paper. First, the sample fitting model is established by using minimal generalized variance as well as the surface fitting model. Second, the defect area of the substrate is determined by analyzing the similarity and membership, which is coded among the pixels by considering the spatial topological structure of the image. Finally, experiments are performed to show that the algorithm proposed in this paper not only has high precision, but also meets industrial real-time requirements for the rapid production of a flexible substrate. Since the method does not depend on the standard template of the original image, it can achieve vision detection effects at high speed and with high precision.