Research on intermittent fault of bond wire under thermal and vibration shock based on simulation and experiments

Abstract

As equipment usage environments become increasingly complex and harsh, the reliability of chips as the core of high-density integrated circuits becomes increasingly important. Bond wires, as weak links, are the focus of reliability research. Traditional research has focused on permanent failures, while intermittent failures have received little attention due to their unpredictable nature, but their existence cannot be ignored. This article simulates temperature shock and vibration environments on bond wires, demonstrating that the dangerous area of bond wires is located at the junction of the gold wire and the chip solder pad. It also explains that intermittent failures are caused by the degradation or potential damage of bond wires that are further damaged when subjected to environmental shocks, with the effective contact area of the damaged area changing with the shock and the resistance changing significantly. Based on the theory of contact resistance, relevant models were constructed for simulation, and the effect of micro-protrusion depth on contact resistance was studied. The article then designed and constructed an experimental circuit to carry out intermittent failure verification tests and studied the characteristics of intermittent failure currents. This research provides theoretical and technical support for the study of intermittent failures in high-density integrated circuits.