High Aspect Ratio Trenches Research Articles

ALd of Metal Fluorides–Potential Applications and Current State

AbstractMetal fluoride thin films are important materials in a multitude of applications. Currently, they are mostly used in optics, but their potential in energy harvesting and storage is recognized as well. Atomic layer deposition (ALD) is an advanced thin film deposition method that has an ever‐increasing role in microelectronics. The assets of ALD are its capability to produce uniform, stoichiometric, and pure films with precise thickness control even on top of complicated structures, such as high aspect ratio trenches. These characteristics can be beneficial in applications of metal fluoride thin films but so far ALD of metal fluorides has remained much less studied and used than ALD of metal oxides, nitrides, sulfides, and pure metals. This review aims to motivate research on ALD of metal fluorides by surveying potential applications for ALD metal fluoride thin films and coatings. The basics of luminescent applications, antireflection coatings, and lithium‐ion batteries will be discussed. Next, the fundamentals of ALD will be presented followed by a comprehensive summary of the metal fluoride ALD processes published so far.

Topography reconstruction of high aspect ratio silicon trench array via near-infrared coherence scanning interferometry

Topography measurement of high aspect ratio trench array using coherence scanning interferometry presents significant challenges because the numerical aperture of detection light is constrained by the trenches. Altering the detection light to penetrate the sample like near-infrared light for silicon could overcome this obstacle, but the trench array spreads the detection light. This study introduces a coherence scanning interferometry model based on three-dimensional point spread function and assuming sample is transparent to detection light, which is realized by integrating rigorous numerical electromagnetic field solution to quantify the modulation aberrations of detection light by transparent trench arrays, and theoretical angular spectrum diffraction utilized for far-field interference imaging. This model facilitates a thorough analysis of the aberrations introduced by trench arrays, encompassing comparisons between trench arrays and a single trench, as well as between the symmetric region of the array and the asymmetric region at the edge. Additionally, an investigation into the impact of unified compensation for low-order aberrations on the topography reconstruction is presented, and we find the sample-induced aberration compensation method utilizing a deformable mirror that we previously proposed for a single trench is still effective confronting trench array. Experimental measurements are performed on silicon trench arrays with the aspect ratio of up to 20:1 and the period of approximately 10 µm to validate the effectiveness of our model and measurement methods, thus providing valuable insights for enhancing high aspect ratio manufacturing.

Bottom-up Gold Filling of Trenches in Curved Wafers

A Bi3+ -stimulated Au electrodeposition process in slightly alkaline Na3AuSO32+Na2SO3 electrolytes has been previously demonstrated for void-free extreme bottom-up filling of high aspect ratio trenches in gratings that are key to advanced X-ray imaging technologies. Effective use of the full area of the gratings with conventional X-ray sources requires they have a finite radius of curvature to align the high aspect ratio Au-filled trenches with divergent X-rays. With that in mind, this work demonstrates bottom-up Au filling in gratings that are attached to curved holders. Contactless mapping of the Au-filled gratings captures residual curvature that is retained after their release from the curved holders (i.e., intrinsic curvature). X-ray diffraction captures the elastic strains in the Si underlying the Au-filled trenches of the grating. Complementary measurements on the surfaces of unpatterned Si wafers mounted on curved holders capture the actual curvatures and strains imposed in the mounted gratings. The gratings, either intrinsically curved or re-bent, provide high visibility across the entire field of view of an X-ray phase contrast imaging system with elastic strains substantially below those in planar gratings bent to the same radius.

Plasma Enhanced Atomic Layer Deposition of Silicon Nitride for Two Different Aminosilane Precursors Using Very High Frequency (162 MHz) Plasma Source.

Plasma enhanced atomic layer deposition (PEALD) of silicon nitride (SiNx) using very high frequency (VHF, 162 MHz) plasma source was investigated at the process temperatures of 100, 200, and 300 °C. Two aminosilane precursors having different numbers of amino ligands, bis(tert-butylamino)silane (BTBAS) and di(sec-butylamino)silane (DSBAS), were used as Si precursors. A comparative study was also conducted to verify the effect of the number of amino ligands on the properties of SiNx film. At all process temperatures, DSBAS, having one amino ligand, performed better than BTBAS in various aspects. SiNx films deposited using DSBAS had lower surface roughness, higher film density, lower wet etch rate, improved electrical characteristics, and higher growth rate than those deposited using BTBAS. With the combination of a VHF plasma source and DSBAS with one amino ligand, the SiNx films grown at 300 °C exhibited low wet etch rates (≤2 nm/min) in a dilute HF solution (100:1 of deionized water:HF) as well as low C content below the XPS detection limit. Also, excellent step coverage close to 100% on high aspect ratio (30:1) trench structures was obtained by using VHF plasma, which could provide sufficient flux of plasma species inside the trenches in conjunction with DSBAS having fewer amino ligands than BTBAS.

Localized protection of high aspect ratio trenches based on the anisotropy manipulation of plasma-polymerized fluoropolymer coating

Microelectronics, microfluidics and energy storage are among the application fields that could take advantage of the localized protection inside deep cavities or textured substrates. However, standard masking techniques used in the industry, such as photolithography, can be limited when applied to wafers with high aspect ratio topography. We have developed a maskless technique based on the anisotropy manipulation of the deposition and etching of a plasma-polymerized fluoropolymer layer, fully protecting the horizontal surfaces of deep trenches while keeping their sidewalls free of any protective layer. We were able to mask trenches with an aspect ratio up to ∼10, and depth of ∼100 μm. As a proof of concept for this localized protection technique, we demonstrate the formation of porous silicon layers (up to 8 μm in thickness) performed by anodization on these walls, while the horizontal surfaces were fully protected.

Molecular layer deposition of alucone in high aspect ratio trenches: The effect of TMA outgassing on step-coverage

Infiltration of trimethylaluminum (TMA) in molecular layer deposition-enabled alucone thin films on planar substrates is a common observation reported in the literature. An insufficient TMA purge time in such cases is often found to lead to a CVD component in the overall film growth due to the reactions between the outgassing TMA and the co-reactant. In this work, the effect of the CVD component on the step coverage of alucone films when grown in high-aspect ratio trenches is studied. The thickness was initially found to increase with increasing distance from the trench aperture before starting to decrease up to the film’s maximum penetration depth. With the support of modeling, the reason behind the observed thickness profile was investigated and attributed to the combination of an increasing outgassing rate of TMA and a decreasing ethylene glycol (EG) concentration along the trench depth. Furthermore, the maximum thickness and the position where it is obtained in the trench are found to depend on TMA and EG doses, TMA purge time, the trench height, and the trench depth. Finally, the possibility of adopting the additional CVD component in film growth for void-less gap fill of 3D trenches is discussed, as well as the suppression of the same CVD component, without compromising the growth rate, by using dimethylaluminum isopropoxide as a substitute for TMA is evaluated.

Mechanism of Bismuth Stimulated Bottom-up Gold Feature Filling

The mechanism underlying -stimulated bottom-up Au filling and self-passivation in trenches and vias in slightly alkaline electrolytes is explored. The impacts of electrolyte components and and potential-dependent kinetic factors on the rate of Au electrodeposition are quantified experimentally. Derived parameters are applied within the surfactant conservation Curvature Enhanced Accelerator Coverage model to simulate the filling of high aspect ratio trenches. It is observed that Bi adsorption accelerates the Au deposition rate with a non-linear dependence occurring around a critical coverage. Further, the impact of electrolyte composition is such that gradients of and derived from reduction of during deposition accentuate deposition farther from the feature opening. These factors and surface area reduction result in Bi enrichment at the bottoms of filling features that localizes active deposition to feature bottoms. Ultimately, weakening of the concentration gradients and associated kinetics as bottom-up feature filling progresses reduces the Bi coverage on the growth front below the critical value and bottom-up growth terminates. Good agreement is observed with key experimental features including the incubation period of conformal deposition, transition to bottom-up growth, subsequent bottom-up filling and finally self-passivation as the growth front nears the field.

Method for Keyhole-Free High-Aspect-Ratio Trench Refill by LPCVD.

In micro-machined micro-electromechanical systems (MEMS), refilled high-aspect-ratio trench structures are used for different applications. However, these trenches often show keyholes, which have an impact on the performance of the devices. In this paper, explanations are given on keyhole formation, and a method is presented for etching positively-tapered high-aspect ratio trenches with an optimised trench entrance to prevent keyhole formation. The trench etch is performed by a two-step Bosch-based process, in which the cycle time, platen power, and process pressure during the etch step of the Bosch cycle are studied to adjust the dimensions of the scallops and their location in the trench sidewall, which control the taper of the trench sidewall. It is demonstrated that the amount of chemical flux, being adjusted by the cycle time of the etch step in the Bosch cycle, relates the scallop height to the sidewall profile angle. The required positive tapering of 88° to 89° for a keyhole-free structure after a trench refill by low-pressure chemical vapour deposition is achieved by lowering the time of the etch step.

(Digital Presentation) Research on Single Wafer RCA Clean in High Aspect Ratio Trenches

I ntroduction. High aspect ratio (AR) processes are widely used in front end of line (FEOL) IC manufacturing. Figure 1 depicts high (AR) trench cleaning process. Polymerization residues produced during the dry etch process will cause many problems such as STI voids in the follow-up process if the residues are not removed. This can lead to lower yield and reduction of chip life[1]. It is difficult to completely clean the residue inside trench with aspect ratio greater than 10.As shown in Figure.2, poor wetting of the liquid in the high AR trench, prevents the cleaning of the whole trench. Typically, the wafer surface can be easily cleaned, however residues remain inside of the trench. The cleaning of polymerization residues inside the trench and eliminating watermarks are the main issues in high (AR) cleaning processes. In this paper, we design an infiltration experiment, polymerization residues cleaning experiment and drying experiment to verify single wafer RCA clean performance on high (AR) trench processes. The verification of the single wafer RCA wafer clean is through yield data. Experimental. In the infiltration experiment, a layer of 500A SiO2 was grown on the high aspect ratios trench wafer. As shown in Table I, This was followed by treating the wafers with different process conditions on ACM single wafer tool. The remaining oxide thickness inside trench was measured by transmission electron microscope (TEM). Figure 3 shows experimental steps.In the polymerization residue cleaning experiment, 7 wafers with trenches after dry etching were treated with different chemical and process mode shown in Table II on ACM single wafer tool. The defect count was measured by the inline defect detection equipment and the scanning electron microscope.(SEM)In the drying experiment, high AR wafers were processed on an ACM single wafer tool, under different drying conditions. The trench wafer were then transferred into a vacuum bag and the air was evacuated. If there is no watermark on wafer surface within 15 minutes, we consider that the wafer has been dried in the macro level.Wafers were split between being cleaned by single wafer RCA clean and by bench RCA clean. The wafers are scanned for defect count on the wafer surface after the cleaning process for both the base line (bench) and the single wafer tool. Finally, we review yield on device completion to check results of single wafer and bench clean. Results. Table I shows the result of dHF infiltration experiment. When the pre rinse DIW time exceeds 30 seconds, the whole trench is soaked by DIW, allowing the dHF to permeate the whole trench, with oxide loss being similar from the top to the bottom of the trench.Table II shows the result of cleaning experiment. ACM Single wafer dHF+SC1 (mega) process can effectively clean the whole trench. Figure 4 and 5 shows defect map and SEM picture after single DHF+SC1(mega).Figure 6 shows the effect of chuck rotation speed and N2 flow rate on wafer drying. Figure 10 shows particle performance under different drying process conditions. Figure 7 shows the inline defect map and SEM after dry process.Figure 8 & 9 show the particle performance after the clean process. No special particle map appears with the single wafer clean process. Fig 10 shows the yield performance after all of the processes are completed. Average yield of single clean process is better than the baseline bench clean process. Table 3 shows detailed yield data from the wafer splits . Conclusion. Infiltration and cleaning experiment result shows that single wafer RCA clean can effectively clean the polymerization residues inside of high aspect ratio trenches. Dry experiment result shows that single wafer process can reduce watermark and particles in the dry step. Inline particle performance and final yield performance shows that single wafer RCA clean is better than baseline bench. Single wafer clean has lower standard deviation than bench clean and SW RCA clean in high (AR) trench process is feasible and effective. References. Xue. Research on High Aspect Ratio TSV Cleaning Technology enhanced by Megasonic[D]. Beijing: University of Chinese Academy of Sciences, 2016.JiHoon Cha, ChangSup Mun, etal. Low Si recess on cleaning process by dilute HF/SC-1 with megasonic[J]. Solid State Phenomena, 2008, 134:209-212.H Wang, Yue Ma, Fuping.Chen, etal. Removal of Fine Particle using SAPS Technology and Functional Water[J]. Solid State Phenomena, 2013, 195:185-190.Dae-Hong EOM, Geun-Bae LIM, etal. Reaction of Ozone and H2O2 in NH4OH Solutionsand Their Reaction with Silicon Wafers[J]. Japanese Journal of Applied Physics, 2004, 43:3335-3339. Figure 1

(Digital Presentation) Research on Single Wafer RCA Clean in High Aspect Ratio Trenches

High aspect ratios trench are commonly used in shallow trench isolation (STI) or Gate Poly-silicon structures by dry etching of a silicon substrate. During the dry etching process, polymerization residues are produced inside the trench. These polymerization residues must be removed before the next deposition process. Watermarks might also form by poor drying after the wet cleaning process of high aspect ratio structures, which can seriously affect the next process. In this paper, we show the performance of single wafer RCA cleaning technology in high aspect ratio structures. Polymer residues can be removed by diluted HF and SC1 with megasonic technology, without the appearance of watermarks after drying. This study focuses on polymerization residues and watermarks using inline defect detection to qualify the performance of single wafer RCA clean. Yield is the final verification for proving the single wafer RCA clean.

Effect of different pulse modes during Cl2/Ar inductively coupled plasma etching on the characteristics of nanoscale silicon trench formation

The etch characteristics of silicon trenches masked with various SiO2/Si3N4pattern distances were investigated using synchronously and asynchronously pulse modes in addition to the continuous wave (CW) mode for Ar/Cl2inductively coupled plasmas. By using synchronously and asynchronously pulse modes instead of CW mode, the selectivity between Si and the mask layer was increased by 2 and 10 times, respectively. Also,the etch rate differences between wide and narrow pattern distance patterns (aspect ratio dependent etching, ARDE) was decreased from 35% to 21 and to 8%,respectively. The increased etch selectivity andreduction of ARDE for the synchronously pulsed mode were related to the increased conduction of Cl radicals/byproductsthrough the high aspect ratio trench, therefore, increased chemisorption/byproduct removal on the silicon trench surface during the pulse-off period. For the asynchronously pulsed mode, the further improved etch selectivity and reduced ARDE were believed to be related to the time separated etch cycle composed of Cl chemical adsorption on the silicon trench surface and the removal of the chemisorbed species by ion bombardment. It is believed that, the asynchronously pulsed plasma etching method can be applicable to various next generation deep nanoscale device fabrication requiring high etch selectivity and low ARDE.

Trench filling with phosphorus-doped monocrystalline and polycrystalline silicon

Optimized epitaxial processes for the filling of deep trenches are mandatory for the fabrication of advanced devices in the microelectronic industry. The use of Selective Epitaxial Growth (SEG) in deep cavities faces multiple issues such as inhomogeneities along the growth direction or defect formation. In this work, the main objective was to develop void-free processes to fill 1:6 up to 1:16 aspect ratio trenches with monocrystalline and polycrystalline Si:P respectively, in a Reduced Pressure – Chemical Vapour Deposition (RP-CVD) reactor. Previous studies suggested the use of a SiH2Cl2 (DCS) + PH3 + HCl chemistry, with an optimization of the DCS/HCl mass-flow ratio (MFR) to conformally fill large and high aspect ratio trenches with monocrystalline Si:P (c-Si:P) while preventing overgrowth at the trench entrance and voids at the bottom. Current studies were first of all conducted on blanket wafers at T = 950 °C and P = 10 Torr, in order to choose the best strategy for varying DCS/HCl MFRs. The P+ ions concentration was quantified and two trends were highlighted depending on the PH3 partial pressure (P(PH3)). For P(PH3) lower than 10-5 Torr, the dopant concentration (in the 1017 - 1018 cm-3 range) increased solely with the phosphine flow and did not depend on the HCl flow. Meanwhile, for PH3 partial pressures higher than 10-5 Torr and thus higher doping levels (between 3x1018 and 2x1019 cm-3), the P+ ions concentration increased with the PH3 flow and decreased as the HCl flow increased. The filling of 1:6 aspect ratio trenches by monocrystalline Si:P was then achieved thanks to a three steps process with various DCS/HCl MFRs. Characterizations showed good crystalline quality together with a steady doping level of 1.3x1018 at cm-3. Further optimizations will however be required to completely suppress voids. Meanwhile, the filling of 1:16 aspect ratio trenches or needles by poly-Si:P was successfully achieved at 10 Torr with a SiH4 + PH3 chemistry, provided that the deposition temperature, 750°C, was low enough to avoid the formation of large poly-Si:P grains, notably at the entrance of such cavities.

The Demonstration of High-Quality Carbon Nanotubes as Through-Silicon Vias (TSVs) for Three-Dimensional Connection Stacking and Power-Via Technology

With the usage of gas ferrocene Fe(C₅H₅)₂ as a reactant, which is different from the traditional thin Fe film, to grow the high-quality carbon nanotubes (CNTs) in the high aspect ratio (AR) trench structure, it has many advantages to be the through-silicon vias (TSVs) material for the three-dimensional (3-D) stacking technology. In this work, we successfully demonstrate the full process flow, including CNT growing, chemical–mechanical planarization (CMP), and wafer temporary bonding for CNTs as TSVs in the 3-D stacking connection. The flexibility for this demonstrated process flow makes the integration of real high dense devices and CNTs as TSVs for the 3-D connection more easily.

(Invited) Selective Area Etching and Doping of GaN for High-Power Applications

Selective-area doping techniques of GaN have been studied intensively for high-power applications. Diffusion or implantation of dopants is a very mature approach in Si and SiC, but it is still under investigation for GaN. Selective area epitaxy and doping is an alternative method to overcome the barrier and is reported by many groups. Two aspects will be discussed, including selective-area etching and non-uniform Mg doping in non-planar regrown trenches.Dry etching has been commonly applied to create high-aspect ratio and smooth trenches, but has also been reported to generate serious optical and electronic defects and impurities on the treated surface. Here, we report using an in-situ etchant, tertiarybutylchloride (TBCl), to replace the dry etching process. In order to demonstrate the effectiveness of TBCl etching, planar PN diodes were grown and fabricated, including continuous, dry-etched, and TBCl-etched and regrown ones. TBCl-etched and regrown device demonstrates electrical properties approach that of the continuous grown diode in the forward and reverse biased conditions.On the other hand, non-uniform doping of Mg was observed in the non-planar regrowth by several groups. With nanoscale characterization technique, atom probe tomography (APT), we identified the origin of the non-uniformity. The Mg concentration is approximately inversely proportional to the growth rate beginning ~20 nm from the regrowth interface. It indicates that the existence of semi-polar facets together with the anisotropy in the growth rate are the origin of non-uniformity. Furthermore, the evolving shape of semi-polar facets could be explained by the kinetic Wulff theorem.

(Invited) Through-Silicon Via Copper Plating and Endpoint Detection

Heterogenous, 2.5D, and 3D integration provide solutions for making microelectronics systems more compact and improving their performance. Cu-filled through-silicon vias (TSVs) are an important interconnect technology for these advanced integration techniques. TSV design and geometry (overall size, aspect ratio, and pitch) depend on the intended microelectronics application. Standard integrated circuit (IC) approaches often utilize high density vias that are achieved through substrate thinning; however, some applications need large-scale vias (≥ 600 µm deep). For example, some microelectromechanical systems (MEMS) applications need full wafer thickness vias due to die thickness specifications, and high-power devices can either employ large-scale vias or via arrays for current requirements and thermal management constraints. Cu deposition fill profile is sensitive to applied voltage or current, electrolyte composition and concentrations, and feature geometry; therefore, deposition processes must be tuned specifically for each via geometry. This work outlines Cu deposition process development and filling results for full wafer thickness TSV geometries in a suppressor-based electrolyte consisting of copper sulfate, sulfuric acid, potassium chloride, and Tetronic 701 suppressor, [i] according to the S-shaped Negative Differential Resistance (S-NDR) mechanism. [ii],[iii] During these TSV filling experiments, unique features in the electrical data were observed that signify completion of Cu plating in the vias. A novel endpoint detection method was derived from these data to determine when vias are filled. [i] Analogous endpoint detection through electrical signals has been previously observed for bottom-up Au filling of high aspect ratio trenches. [iv] During voltage-controlled via filling, as the Cu electrodeposit approaches the top of the TSVs, current can be monitored for a slight rise (due to increased metal ion transport and plating rate high up in the features), followed by a current local minimum (caused by adsorbed suppressor molecules that impede Cu deposition at the top of the vias). These characteristic features in the electrical data can be used to determine via filling completion. A similar technique can be used during current-controlled filling, where voltage data are monitored for a voltage maximum, which indicates that the Cu electrodeposit has reached the top of the features. Current work involves development of an automated method to recognize these electrical endpoint signals and terminate deposition when the vias are filled. This endpoint detection method has potential to greatly enhance microelectronics manufacturing by providing geometry-independent process control, improving manufacturing repeatability, decreasing sensitivity to changes in electrolyte over time, and reducing the time involved in subsequent processing steps through minimizing Cu overburden formation.Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. SAND2021-5013 A [i] R. P. Schmitt et al 2020 J. Electrochem. Soc. 167 162517. [ii] D. Josell and T. P. Moffat 2016 ECS Trans. 75 15. [iii] D. Josell and T. P. Moffat 2018 J. Electrochem. Soc. 165 D23. [iv] S. Ambrozik et al 2019 J. Electrochem. Soc. 166 D443.

Effect of Inductively Coupled Electromagnetic Field on Bottom Oxide Etch in a High Aspect Ratio Trench

CMOS optical sensors devices are becoming increasingly important and popular for many different applications. Some of these devices are fabricated starting from SOI wafers and using semiconductor manufacturing techniques.A common feature of the CMOS sensors is the isolating trench that protects the device from electrical noise. In our particular application, the trench is much deeper than usual, in order to isolate the sensor also from stray light interference.In the present paper we describe the multistep etch process used to create the trench rounding all around the sensor chip.First a silicon oxide HM (Hard Mask) is etched in a CCP (Capacitively Coupled Plasma) chamber with a recess in silicon as shallow as possible to preserve the photo-resist; then an ICP (Inductively Coupled Plasma) reactor is used to etch 23um silicon etch, landing onto a 1um BOX (Buried OXide) layer.Finally the BOX is etched with a dedicated step followed by a second silicon etch to get a deeper isolating trench, both steps performed in the same ICP chamber.The trench layout is lined internally by a closed-loop metal line that is buried in the HM stack.While working on the process development, an unexpected asymmetrical slope of the BOX sidewalls was observed.This has prompted us to focus the attention to the BOX etch and the effect that an applied electromagnetic field and its interaction with the metal line, exert on the etch behaviour.The plasma chamber employed for the BOX and silicon etch is a reactor with a top ICP source and a platen electrode, powered by two independent RF generators, both at 13.56MHz. The peculiarity of this etcher is to have an additional coil – where a high value continuous electrical current flows - used to modulate the plasma shape in the chamber.The initial BOX etch recipe applied had been used successfully in the past for similar scopes. However when it was employed for this specific application, the subsequent XSEM inspection highlighted an asymmetrical shape of the sidewalls, in different locations on the wafer. In particular the sidewall opposite to the metal line always shows an accentuated slope, compared to the other that is straight and vertical.Starting from this observation, we assumed there was an influence of the presence of the metal line during the BOX etch. The hypothesis is that the electromagnetic field generated by the additional coil of the etcher, couples with the metal lines, acting as spires on the wafer, resulting in a local electromagnetic field that has an effect on electron and ion trajectories during the etch. The result of this is the local asymmetry of the sidewalls.To prove this hypothesis, three additional tests have been executed, so to have four distinct conditions: 1) BOX etch with Coil Current ON and metal spires buried in the HM stack; 2) BOX etch with Coil Current OFF and metal spires buried in the HM stack;3) BOX etch with Coil Current ON and NO metal spires buried in the HM stack; 4) BOX etch with Coil Current OFF and NO metal spires buried in the HM stack.The results of these tests confirm the influence of the electromagnetic field generated by the additional coil, since it gives asymmetric features in both conditions 1) and 3), and not in conditions 2) and 4). At the same time the coupling with the metal spires has an influence too, since it gives a local asymmetry in condition 1) and a wafer level asymmetry in condition 3). Figure 1

Effect of Inductively Coupled Electromagnetic Field on Bottom Oxide Etch in a High Aspect Ratio Trench

CMOS optical sensors devices are becoming increasingly important and popular for many different applications. Some of these devices are fabricated starting from SOI (Silicon On Insulator) wafers and using semiconductor manufacturing techniques. A common feature of the CMOS sensors is the isolating trench that protects the device from electrical noise. We report on the multistep etch process development to fabricate trenches deeper than usual, in order to isolate the sensor also from stray light interference. We focus the attention on unexpected features that originated during the Buried Oxide (BOX) etch.

Ion assisted near-complete filling of high aspect ratio trenches for 3-D neutron detectors

A single-step process has been developed for the conformal deposition of boron carbide in high aspect ratio trenches fabricated in an n-type (111) silicon substrate. Plasma enhanced chemical vapor deposition was used to deposit boron carbide from ortho-carborane (OC2B10H12) precursor mixed with helium and argon gas. The depositions were carried out under substrate self-bias conditions to achieve a high fill factor using forward-directed ions. Nearly complete filling of 25 µm deep trenches with high-aspect ratio (> 6:1) via conformal coating of side walls has been confirmed from cross-sectional scanning electron microscopy studies. The results presented in this article establish that the process technology developed for achieving conformal deposition of the neutron stopping layer is suitable for the fabrication of Silicon p-i-n based three-dimensional thermal neutron detectors with high neutron detection efficiency.

Characteristics of silicon nitride deposited by very high frequency (162 MHz)-plasma enhanced atomic layer deposition using bis(diethylamino)silane

Silicon nitrides, deposited by capacitively coupled plasma (CCP)-type plasma enhanced atomic layer deposition (PEALD), are generally applied to today’s nanoscale semiconductor devices, and are currently being investigated in terms of their potential applications in the context of flexible displays, etc. During the PEALD process, 13.56 MHz rf power is generally employed for the generation of reactive gas plasma. In this study, the effects of a higher plasma generation frequency of 162 MHz on both plasma and silicon nitride film characteristics are investigated for the purpose of silicon nitride PEALD, using bis(diethylamino)silane (BDEAS) as the silicon precursor, and N2 plasma as the reactant gas. The PEALD silicon nitride film deposited using the 162 MHz CCP exhibited improved film characteristics, such as reduced surface roughness, a lower carbon percentage, a higher N/Si ratio, a lower wet etch rate in a diluted HF solution, lower leakage current, and higher electric breakdown field, and more uniform step coverage of the silicon nitride film deposited in a high aspect ratio trench, as compared to silicon nitride PEALD using 13.56 MHz CCP. These improved PEALD silicon nitride film characteristics are believed to be related to the higher ion density, higher reactive gas dissociation, and lower ion bombardment energy to the substrate observed in N2 plasma with a 162 MHz CCP.

Thin Films of Layered-MoS2: ALD of Molybdenum and Sulfurization a Novel Approach

Thin layers of two dimensional (2D) materials mainly transition metal dichalcogenides (TMDs) and more specifically ultra-thin layered-MoS2 semiconductor possess exceptional properties such as electrical, optical, magnetic, mechanical and chemical properties. This allows the exploration of internal quantum degrees of freedom of electrons and their potential for use in semiconductor microelectronics, optoelectronic, energy, and sensor and detector applications. These exciting results are being achieved mostly by using exfoliation of flecks from bulk MoS2 crystal. However, the biggest challenge in realizing TMDs full potential has been the lack of scalable material synthesis methods for such films with high uniformity, conformality and interfacing with other materials such as oxides, metals and its process compatibility. Among the various thin film deposition methods, atomic layer deposition (ALD) offers the best combination of precisely controlled layer-by-layer thin film growth at low temperature with very high conformality on complex substrates. Here we will present the growth of layered-MoS2 thin films. To grow high quality layered–MoS2 thin films, we have developed an ALD-based two step processing approach: firstly the growth of well controlled ultra-thin layer of Mo metal using ALD followed by the sulfurization of the ALD Mo layer at various temperatures. This two-steps processing results in high quality layered-MoS2 thin films on large substrates. For the Mo ALD process we used molybdenum hexafluoride (MoF6) and Si2H6 precursors. We used in-situ QCM measurements to study interfacial and nucleation effects in the formation of continuous ultra-thin metal layer of Mo. The composition of both the ALD Mo and the layered MoS2 layers was determined by X-ray photoelectron spectroscopy (XPS). Further, cross-sectional transmission electron microscopy (TEM) was performed to confirm the formation of layered MoS2 on high aspect ratio trenches and Raman analysis to verify the signature of E12g blue shift and A1g red shift in the MoS2 structure. Here, we will discuss the details of the two-step thin film growth process for creating layered MoS2 layers via ALD Mo and subsequent sulfurization as well as the properties of the MoS2 films.