(Invited) Through-Silicon Via Copper Plating and Endpoint Detection

Abstract

Heterogenous, 2.5D, and 3D integration provide solutions for making microelectronics systems more compact and improving their performance. Cu-filled through-silicon vias (TSVs) are an important interconnect technology for these advanced integration techniques. TSV design and geometry (overall size, aspect ratio, and pitch) depend on the intended microelectronics application. Standard integrated circuit (IC) approaches often utilize high density vias that are achieved through substrate thinning; however, some applications need large-scale vias (≥ 600 µm deep). For example, some microelectromechanical systems (MEMS) applications need full wafer thickness vias due to die thickness specifications, and high-power devices can either employ large-scale vias or via arrays for current requirements and thermal management constraints. Cu deposition fill profile is sensitive to applied voltage or current, electrolyte composition and concentrations, and feature geometry; therefore, deposition processes must be tuned specifically for each via geometry. This work outlines Cu deposition process development and filling results for full wafer thickness TSV geometries in a suppressor-based electrolyte consisting of copper sulfate, sulfuric acid, potassium chloride, and Tetronic 701 suppressor, [i] according to the S-shaped Negative Differential Resistance (S-NDR) mechanism. [ii],[iii] During these TSV filling experiments, unique features in the electrical data were observed that signify completion of Cu plating in the vias. A novel endpoint detection method was derived from these data to determine when vias are filled. [i] Analogous endpoint detection through electrical signals has been previously observed for bottom-up Au filling of high aspect ratio trenches. [iv] During voltage-controlled via filling, as the Cu electrodeposit approaches the top of the TSVs, current can be monitored for a slight rise (due to increased metal ion transport and plating rate high up in the features), followed by a current local minimum (caused by adsorbed suppressor molecules that impede Cu deposition at the top of the vias). These characteristic features in the electrical data can be used to determine via filling completion. A similar technique can be used during current-controlled filling, where voltage data are monitored for a voltage maximum, which indicates that the Cu electrodeposit has reached the top of the features. Current work involves development of an automated method to recognize these electrical endpoint signals and terminate deposition when the vias are filled. This endpoint detection method has potential to greatly enhance microelectronics manufacturing by providing geometry-independent process control, improving manufacturing repeatability, decreasing sensitivity to changes in electrolyte over time, and reducing the time involved in subsequent processing steps through minimizing Cu overburden formation.Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. SAND2021-5013 A [i] R. P. Schmitt et al 2020 J. Electrochem. Soc. 167 162517. [ii] D. Josell and T. P. Moffat 2016 ECS Trans. 75 15. [iii] D. Josell and T. P. Moffat 2018 J. Electrochem. Soc. 165 D23. [iv] S. Ambrozik et al 2019 J. Electrochem. Soc. 166 D443.