Heterojunction Tunnel Research Articles

Quantum mechanical analysis of 2D transition metal dichalcogenide material based vertical heterojunction tunnel FET

In this work, a single layer n-doped MoS2 and p-doped WTe2 based vertical heterojunction tunnel FET has been investigated through a well-organized quantum mechanical approach. The key outcome is the design criteria of the device for low subthreshold swing keeping its length as short as possible. Inter-coupled real space model Hamiltonian of the device is formed by introducing the coupling energy of the WTe2 valence band and the MoS2 conduction band in the overlap region. Here, MATLAB based self-consistent analysis is used to numerically solve the device by coupling Schrödinger and Poisson equations taking into account the plane dependence of permittivity in 2D transition metal dichalcogenide materials. For 15 nm channel overlap length and 15 nm gate extension length, a subthreshold slope of as low as 10 mV/decade has been obtained. For 20 nm channel overlap length, an ON current of 18 µA/μm has been obtained as well. The effect of the top gate extension, overlap length, and dielectric layer thickness over the ON and OFF state currents has been explained from the viewpoint of device physics. Thus, the framework presented will help designers to optimize the device for improved performance.

A comprehensive analysis of Auger generation impacted planar Tunnel FETs

Tunnel Field Effect Transistors (TFETs) are known to be compromised by higher order processes that downgrade their performance compared to ballistic projections. Using a quasi-analytical model that extends the chemistry based Simmons equation to include finite temperature effects, potential variations and scattering, we exhibit that non-idealities like trap-assisted tunneling and Auger generation can explain the observed performance discrepancy. In particular, Auger generation is the dominant leakage mechanism in TFETs at low trap densities. Our studies suggest that possible ways of reducing Auger generation rate are reducing source carrier concentration and increasing the valence band transport effective mass of the source material. In this paper, we specifically investigate the impact of variations of these factors on device performance of staggered bandgap planar III-V heterojunction Tunnel FETs.

Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

This study investigated the device optimization scheme of a double-gate hetero-junction tunnel FET, which was expected to improve circuit performance. A thinner channel with a stronger electric field increases the tunnel on-current. Conversely, a thin channel results in a larger quantum sub-band energy and an effective bandgap, which decreases the tunnel on-current. Such tradeoffs are clarified by considering the quantum effects in a device simulation. Furthermore, the gate capacitance behavior, identified via device simulation, was considered, and it demonstrates that the double-gate hetero-junction tunnel FET has a substantial capacitance merit compared to CMOS transistors. The early stages of our work used the intrinsic delay for device optimization, as defined in the international technology roadmap for semiconductors. However, based on the comparison with the speed evaluation results of the ring oscillator, the device optimization scheme was improved. This was achieved by adopting a new effective delay index, based on the effective on-currents and effective gate capacitances. Studies on the CMOS device design also applied the concept of effective on-current; however, the design method presented herein is novel in that it introduced the concept of effective gate capacitance.

Analysis of Noise-Immune Dopingless Heterojunction Bio-TFET Considering Partial Hybridization Issue

A dielectric modulated (DM) dual-sided dopingless (DL) GaAs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> /In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As hetero-junction (HJ) Tunnel FET (DM-DDL-HTFET) based label-free biosensor architecture having hetero-gate-dielectric (HGD) has been offered. Here, virtual pocket of N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -category with differing electronic concentration (Ne) has been realized through the adjustment of source-sided-channel length (LSC) below the gate region. Primarily, the optimized structure has been investigated considering energy-band gap, mole fraction of HJ material and gate-to-source spacer thickness (Lgap,S). Next, the efficiency of optimized DDL-HTFET model excluding nano-gap has been juxtaposed with the Si-based TFET contenders. The effect on Ne, surface potential (ψ), drain-current (IDS), and their equivalent sensitivity have been analyzed by the ATLAS device simulator considering the steric hindrance issues. 37.54% and 54% improvement in threshold voltage sensitivity can be obtained for DM-DDL-HTFET over single side DL-SiTFET (DM-SDL-SiTFET) due to variation of oxide layer thickness (Tox) and source-side dielectric material respectively. Moreover, DM-DDL-HTFET offers 58.64% (42.18%) and 44.44% (73.33%) inferior minimum noise figure and noise conductance over DM-SDL-SiTFET at 50 (250) GHz frequency correspondingly after immobilization of APTES biomolecules.

Performance Analysis of Double Gate Hetero Junction Tunnel Fet

In this paper, a novel heterojunction tunnel field-effect transistor (HTFET) using Sentaurus technology computer-aided design (TCAD) simulations has been presented. The InAs/GaSb compound materials are used in both single gate heterojunction TFET (SG-HTFET) and Double gate heterojunction TFET (DG-HTFET) with SiO2 gate oxide layer to increase performance of the device.The implemented SG-HTFET and DG-HTFET device are increase the TFET's cross-sectional tunnel area. This result develops the subthreshold swing (SS) by 2.45 times, drive current (ION) is close to 10-6 A/µm, leakage current (IOFF) is close to 10-17 A/µm and also diminish the ambipolarity of the device compared to the TFET.

Contribution of the Doping of the Lower Window Layer to Improve the Performances of the Tandem Solar Cell

Each layer of the tandem solar cell, its doping or its thickness, plays a primary task in improving the conversion efficiency. The optimization of the doping of the window layer of the lower solar cell of the tandem cell contributes to the reduction of the cost of the manufacture of its cells. The objective of this work is to show the role of doping the lower window layer on the performances of tandem CS in InGaP / GaAs with a tunnel heterojunction. For this a simulation is carried out using the Atlas-Silvaco simulator. It is specially designed for 2D and 3D modeling of components based on the physics of semiconductors, including electrical, optical and thermal properties The adapted structure is essentially composed of an upper cell in InGaP and a lower cell in GaAs. Between the two upper and lower cells, there is a heterojunction tunnel) P ++ N ++. The structure studied is composed of a thin window layer heavily doped with the materialIn0.629Al0.159Ga0.371P0.841 .Our simulation showed that, for an illumination of AM 1.5 and at room temperature, the parameters, such as the short-circuit current and the conversion efficiency, improve with the doping of the upper window layer.The best conversion efficiency is 24.2343% for a doping of 8x1018 cm-3.

Counteracting the Photovoltaic Effect in the Top Intergenerator Part of GaInP/GaAs/Ge Solar Cells

The “top” intergenerator part situated between the GaInP and GaAs subcells (electric power generators) is analyzed. The shape of the light current–voltage characteristics and the Voc–Jsc (open-circuit voltage–short-circuit current) dependence are examined. It is found that the p+–n+ tunnel heterojunction situated in the “top” intergenerator part can operate as a photoelectric source counteracting the base p–n junctions. In this case, the Voc–Jsc characteristic has a descending part, and a sharp jump can be observed. This undesirable effect becomes weaker with increasing peak current of the tunnel junction.

Si/GaAs Hetero Junction Tunnel FET: Design and Investigation

Si/GaAs Hetero Junction Tunnel FET: Design and Investigation

Design, Implementation and Power Analysis of Low Voltage Heterojunction Tunnel Field Effect Transistor based Basic 6T SRAM Cell

The battery-powered mobile devices limited energy process by MOSFET's due to subthreshold swing and underneath 60mV/dec for ultra fewer energy applications. This research introduces the layout and execution of a mobile electronic device full-on-presence, extended Miller potential, and reduced HETT subthreshold swing effectiveness has been compared with MOSFET's Gate oxide blending on source can increase channel tunneling in this work. To enhance transistor line, Miller capacitance impact can be decreased by using low band offset equipment and small power product of metals such as Ge or SiGe. This, in turn, leads to stronger transistor efficiency features. The proposed layout and execution of HETT includes manufacturing of mutually NHETT and PHETT and efficiency analyzes of both NHETT and PHETT. Concerning the fundamental and skeletal distinctions among MOSFET and HETT to promote the utilization of MOSFET instead of HETT, the benefits and constraints of both NHETT and PHETT have been detailed. HETT's construction process is by no means entirely different, suitable for the scheme of MOS method and suitable for transportable motorized applications. HETT provides the 6T SRAM cell electricity evaluation and the output was reviewed using standard SRAM cell. The average power, maximum power and minimum power of SRAM by using both MOSFET and HETT are obtained and compared. The mask layers of HETT fabrication is not that much difference than MOSFET and hence CMOS MOSFET fabrication is friendly to HETT fabrication. In future, the combination of both CMOS MOSFET and HETT are used, CMOS technology for digital logic and HETT for semiconductor memory applications.

Electrical Characteristics Assessment on Heterojunction Tunnel FET (HTFET) by Optimizing Various High-κ Materials: HfO2/ZrO2

In this paper, DC performance of double gate tunnel field effect transistor with heterojunction has been assessed by various III-V compound semiconductor materials using 2-D Technology Computer Aided Design (TCAD) simulations. Different hetero high-κ dielectric materials like HfO2, ZrO2 have been incorporated to achieve better electrical characteristics, viz. high ON-state current drivability, improved switching ratio and high tunneling probability. In this work, lower band gap materials have been used as hetero gate dielectric to enhance mobility using band to band tunneling (BTBT), transconductance and steeper subthreshold-slope. The heterojunction TFET (HTFET) then incorporated with various hetero dielectrics (high-κ and low-κ combination), where the ZrO2 – SiO2 combination of dielectric having thickness of 2 nm both in front and back gate, attains maximum value of ION as 1.522 × 10-5 A/μm. The subthreshold swing (ss) has also been recorded best as 23.93 mV/dec in comparison with conventional homo dielectric i.e. SiO2-SiO2 oxide throughout the 50 nm channel of HTFET as 34.22 mV/dec, can serve as better alternative tunnel FETs in low power logic applications.

An electrostatic analytical modeling of high-k stacked gate-all-around heterojunction tunnel FETs considering the depletion regions

This paper deals with the analytical modelling of high-k stacked Gate-All-Around Heterojunction Tunnel Field Effect Transistor (GAA-HJTFET) considering the depletion regions. The surface potential is derived from 2D Poisson’s Equation using the Parabolic Approximation Methodology and the Electric field is obtained by differentiating the surface potential. The drain current is obtained by considering volume of the device, shortest tunnelling path using the Kane’s Model. Due to heterojunction of the SiGe the energy band of the device move downwards to the intrinsic region because of which ION current improves, supress ambipolar behaviour of the device and reduces subthreshold swing. ION-IOFF ratio obtained from the device is 1010. Threshold voltage, transconductance is calculated using drain current equation where the threshold voltage is between 0.7 and 0.8 V and transconductance is 280 µA/mV. The results obtained are validated using ATLAS TCAD Simulation Tool.

An Analytical Drain Current Model for the Cylindrical Channel Gate-All-Around Heterojunction Tunnel FETs

In this paper, we present analytical models which are valid in all regions of operation and can accurately predict the potential profile and the output, as well as the transfer characteristics of the gate-all-around heterojunction tunnel field-effect transistors. Our potential model takes into account the charge carriers in the channel, as well as the space charges in the depletion regions of the two reservoirs. Later, this potential model is utilized to calculate the band-to-band tunneling generation rates at any spatial coordinate in the tunneling volume. Next, these rates are integrated over tunneling volume to find the total tunneling current. This leads to an analytical model for the drain current. We validate our models against the data obtained via numerical simulations for several common heterojunction tunnel devices at various geometries and bias conditions.

ZnO/Si and ZnO/Ge bilayer tunneling field effect transistors: Experimental characterization of electrical properties

In this study, we experimentally characterize the electrical properties of a bilayer tunneling field effect transistor (TFET) with a heterotunneling junction composed of an oxide-semiconductor source and a group-IV-semiconductor channel in detail. Bilayer TFETs with a n-ZnO/p-Si or n-ZnO/p-Ge heterotunneling junction with type-II energy band alignment are fabricated by pulsed-laser deposition of a zinc oxide (ZnO) layer on Si or Ge with various impurity concentrations. The evidence of the TFET operation are examined through a comparison of the electrical characteristics with ZnO thin film transistors as well as the tunneling junction area dependence, which is important for clarifying the operating mechanism. The source material and its impurity concentration significantly affect the Id-Vg and Id-Vd characteristics of the bilayer TFETs, with reducing tunneling barrier height and tunneling distance. The influence of the source materials and doping concentrations is also studied by simulation. As a result, the minimum subthreshold swing (SS) of 71 mV/dec and the Ion/Ioff ratio of ∼6 × 108 have been achieved for n-ZnO/p-Si and n-ZnO/p-Ge TFETs, respectively, at room temperature. It is also found that the fabricated TFET shows weak measurement temperature dependencies of Ion and SS, which are expected for TFETs, with the extremely low off-state current in a fA/μm range. These characterizations of the electrical characteristics of the bilayer TFETs are important not only for a physical understanding of the operating mechanism but also for further improvement of the TFET performance.

Bilayer tunneling field effect transistor with oxide-semiconductor and group-IV semiconductor hetero junction: Simulation analysis of electrical characteristics

Operation mechanisms and electrical characteristics of tunneling field-effect transistors (TFETs) employing a hetero tunneling junction by utilizing an n-type oxide-semiconductor (OS) and a p-type group-IV-semiconductor are comprehensibly analyzed. Gate-normal band-to-band tunneling (BTBT) has high potential for the superior TFET performance such as high on-state current and small sub-threshold swing (S.S.). Additionally, a hetero tunneling junction with type-II energy band alignment is promising to exponentially increase tunneling probability with keeping small off-state current. Therefore, in this study, we investigate the impact of key material and device parameters such as energy band alignment of source/channel regions and thickness of the OS channel layer or gate insulator based on technology computer aided design (TCAD) simulation. The gate-controlled uniform band bending along the source-drain direction realizes uniform BTBT in the entire region of the hetero tunneling junction. Also, the reduction of the tunneling barrier height, which is continuously controlled by the conduction band minimum of the OS-channel and the valence band maximum of the IV-source, is effective to increases on-state current and decrease S.S. value. On the other hand, the thicknesses of OS channel layer and gate insulator have strong influences on tunneling probability and threshold voltage. Therefore, the sub-threshold characteristics of TFETs are sensitive to non-uniformities in the tunneling junction such as channel thickness fluctuation and surface potential fluctuation at the metal-oxide-semiconductor (MOS) interfaces. These numerical analyses of the device operation are essentially important to understand the effects of key device parameters on the TFET performance and to realize the superior electrical performance.

MOVPE-grown AlGaN-based tunnel heterojunctions enabling fully transparent UVC LEDs

We report on AlGaN-based tunnel heterojunctions grown by metalorganic vapor phase epitaxy enabling fully transparent UVC LEDs by eliminating the absorbing p-AlGaN and p-GaN layers. Furthermore, the electrical characteristics can be improved by exploiting the higher conductivity of n-AlGaN layers as well as a lower resistance of n-contacts. UVC LEDs with AlGaN:Mg/AlGaN:Si tunnel junctions exhibiting single peak emission at 268 nm have been realized, demonstrating effective carrier injection into the AlGaN multiple quantum well active region. The incorporation of a low band gap interlayer enables effective tunneling and strong voltage reduction. Therefore, the interlayer thickness is systematically varied. Tunnel heterojunction LEDs with an 8 nm thick GaN interlayer exhibit continuous-wave emission powers >3 mW near thermal rollover. External quantum efficiencies of 1.4% at a DC current of 5 mA and operating voltages of 20 V are measured on-wafer. Laterally homogeneous emission is demonstrated by UV-sensitive electroluminescence microscopy images. The complete UVC LED heterostructure is grown in a single epitaxy process including in situ activation of the magnesium acceptors.

AsP/InSe Van der Waals Tunneling Heterojunctions with Ultrahigh Reverse Rectification Ratio and High Photosensitivity

AbstractVan der Waals heterojunctions made of 2D materials offer competitive opportunities in designing and achieving multifunctional and high‐performance electronic and optoelectronic devices. However, due to the significant reverse tunneling current in such thin p–n junctions, a low rectification ratio along with a large reverse current is often inevitable for the heterojunctions. Here, a vertically stacked van der Waals heterojunction (vdWH) tunneling device is reported consisting of black arsenic phosphorus (AsP) and indium selenide (InSe), which shows a record high reverse rectification ratio exceeding 107 along with an unusual ultralow forward current below picoampere and a high current on/off ratio over 108 simultaneously at room temperature under the proper band alignment design of both the Schottky junction and the heterojunction. Therefore, the vdWH tunneling device can function as an ultrasensitive photodetector with an ultrahigh light on/off ratio of 1 × 107, a comparable responsivity of around 1 A W−1, and a high detectivity over 1 × 1012 Jones in the visible wavelength range. Furthermore, the device exhibits a clear photovoltaic effect and shows a spectral detection capability up to 1550 nm. The work sheds light on developing future electronic and optoelectronic multifunctional devices based on the van der Waals integration of 2D materials with designed band alignment.

High On-Current Ge-Channel Heterojunction Tunnel Field-Effect Transistor Using Direct Band-to-Band Tunneling.

The main challenge for tunnel field-effect transistors (TFETs) is achieving high on-current (Ion) and low subthreshold swing (SS) with reasonable ambipolar characteristics. In order to address these challenges, Ge-channel heterostructure TFET with Si source and drain region is proposed, and its electrical characteristics are compared to other TFET structures. From two-dimensional (2-D) device simulation results, it is confirmed that the Si/Ge heterostructure source junction improves Ion and SS characteristics by using the direct band-to-band tunneling current. Furthermore, the proposed structure shows suppressed ambipolar behavior since the Ge/Si heterostructure is used at the drain junction.

Asymmetric gated Ge-Si&lt;SUB align="right"&gt;0.7Ge&lt;SUB align="right"&gt;0.3 nHTFET and pHTFET for steep subthreshold characteristics

The miniaturisation of transistors imposes thermal limits on MOSFET structures due to increase in leakage current and static power consumption per unit area of chip below 20 nm technology node. Tunnel FET has potential to reduce static power consumption to design below 20 nm technology within thermal limits thus increases the scope of future scaling trends. A new asymmetric Ge-Si0.7Ge0.3 hetero-junction tunnel FET (HTFET) is proposed with different oxide thickness from source and drain side. The asymmetric Ge-Si0.7Ge0.3 HTFET has steep subthreshold characteristic, low DIBL with high ION/IOFF current ratio for operating voltage less than 1V. The proposed design can be fabricated easily due to the similar lattice structure of Ge and Si. The ION/IOFF current ratio greater than 108 is achieved for gate length of 15 nm in nHTFET having Pt/HfO2 as gate contact and oxide material. The lowering of parasitic BJT effect in OFF state condition is also achieved in the same.

Asymmetric Gated Ge-Si0.7Ge0.3 nHTFET and pHTFET for Steep Subthreshold Characteristics

The miniaturisation of transistors imposes thermal limits on MOSFET structures due to increase in leakage current and static power consumption per unit area of chip below 20 nm technology node. Tunnel FET has potential to reduce static power consumption to design below 20 nm technology within thermal limits thus increases the scope of future scaling trends. A new asymmetric Ge-Si0.7Ge0.3 hetero-junction tunnel FET (HTFET) is proposed with different oxide thickness from source and drain side. The asymmetric Ge-Si0.7Ge0.3 HTFET has steep subthreshold characteristic, low DIBL with high ION/IOFF current ratio for operating voltage less than 1V. The proposed design can be fabricated easily due to the similar lattice structure of Ge and Si. The ION/IOFF current ratio greater than 108 is achieved for gate length of 15 nm in nHTFET having Pt/HfO2 as gate contact and oxide material. The lowering of parasitic BJT effect in OFF state condition is also achieved in the same.

Alloy Engineered Nitride Tunneling Field-Effect Transistor: A Solution for the Challenge of Heterojunction TFETs

Being fundamentally limited to a current–voltage steepness of 60mV/dec, MOSFETs struggle to operate below 0.6 V. Further reduction in ${V}_{\text {DD}}$ and, consequently, power consumption can be achieved with novel devices, such as tunneling transistors (TFETs) that can overcome this limitation. TFETs, however, face challenges with low ON-current leading to slow performance. TFETs made from III-nitride heterostructures are quite promising in this regard. The lattice mismatch induces a piezoelectric polarization field in a nitride heterojunction that can boost the ON-current. However, it is shown here that the carrier thermalization at the heterointerface degrades the subthreshold characteristics. Therefore, a good design should minimize the number of confined quantum well (QW) states at the heterointerface so as not to degrade the subthreshold characteristics while maintaining the lattice mismatch induced polarization to boost the ON-current. We show here that an InAlN QW on an InGaN substrate alloy engineered TFET design is promising to fulfill these requirements. Proper engineering of the alloy mole fractions and the width of the well can eliminate (or at least minimize) the undesired thermalization effects and, at the same time, provide a lattice mismatch to induce a piezoelectric field for boosting the ON-current. We have used a suitable atomistic quantum transport model to simulate these devices. The model accounts for the different mechanisms that are involved, and captures realistic scattering thermalization effects. This model has been benchmarked in our earlier work with experimental measurements of nitride tunneling heterojunction diodes and is used here to optimize the alloy engineered nitride TFET.