Heterogeneous MPSoCs Research Articles

Modeling and Controlling Many-Core HPC Processors: an Alternative to PID and Moving Average Algorithms

The race towards performance increase and computing power has led to chips with heterogeneous and complex designs, integrating an ever-growing number of cores on the same monolithic chip or chiplet silicon die. Higher integration density, compounded with the slowdown of technology-driven power reduction, implies that power and thermal management become increasingly relevant. Unfortunately, existing research lacks a detailed analysis and modeling of thermal, power, and electrical coupling effects and how they have to be jointly considered to perform dynamic control of complex and heterogeneous mpsoc. To close the gap, in this work, we first provide a detailed thermal and power model targeting a modern hpc mpsoc. We consider real-world coupling effects such as actuators’ non-idealities and the exponential relation between the dissipated power, the temperature state, and the voltage level in a single processing element. We analyze how these factors affect the control algorithm behavior and the type of challenges that they pose. Based on the analysis, we propose a thermal capping strategy inspired by Fuzzy control theory to replace the state-of-the-art PID controller, as well as a root-finding iterative method to optimally choose the shared voltage value among cores grouped in the same voltage domain. We evaluate the proposed controller with model-in-the-loop and hardware-in-the-loop co-simulations. We show an improvement over state-of-the-art methods of up to \(5\times\) the maximum exceeded temperature while providing an average of \(3.56\%\) faster application execution runtime across all the evaluation scenarios.

A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs

Sound techniques for mapping soft real-time applications to resources are indispensable for meeting the application deadlines and minimizing objectives such as energy consumption, particularly on heterogeneous MPSoC architectures. For applications with input-dependent workload variations, static mappings are not able to sufficiently cope with the run-time variation, which can lead to deadline misses or unnecessary energy consumption. As a remedy, hybrid application mapping (HAM) techniques combine a design-time optimization with run-time management that adapts the mappings dynamically to the changes of the arriving input. This paper focuses on scenario-based HAM techniques. Here, the application input space is systematically clustered such that data inside the same scenario exhibit similar characteristics concerning workload when being processed under the same operating points. This static clustering of the input space into data scenarios has proven to be a good abstraction layer for simplifying the design and employment of high-quality run-time managers. However, existing state-of-the-art scenario-based HAM approaches neglect or underutilize the synergistic interplay between mapping selection and the usage of dynamic voltage/frequency scaling (DVFS) when adapting to workload variation. By combining mapping and DVFS selection, variations in the input can be either compensated by a complete re-mapping of the application, evoking a potential high reconfiguration overhead or by just changing the DVFS settings of the resources, offering a low-overhead adaptation alternative and thus significantly reducing the necessary overhead compared to DVFS-agnostic HAM. Furthermore, DVFS enables a fine-grained adaptation of a mapped application to the input data variation, e.g., by slowing down tasks with no impact on the end-to-end latency for the current input using low-frequency DVFS settings. It is shown that this combined approach can save even more energy than a pure mapping adaptation scheme, especially in the presence of data scenarios. In particular, scenario-based design operates as a catalyst for eliciting the synergies between a combined DVFS and mapping optimization and the peculiarities inside a data scenario, i.e., exploiting the commonalities inside a data scenario by perfectly tailored DVFS settings and task mapping. In this scope, this paper proposes two supplementary scenario-based DVFS-aware HAM approaches that consistently outperform existing state-of-the-art mapping approaches in terms of the number of deadline misses and energy consumption as we demonstrate in an empirical study on the basis of four different applications and three different architectures. It is also shown that these benefits still apply to target architectures with increasing mapping migration overheads, thwarting frequent mapping reconfigurations.

Split Boot—True Network-Based Booting on Heterogeneous MPSoCs

In the context of the High-Luminosity (HL) upgrade of the LHC, many custom ATCA electronics boards are being designed containing heterogeneous System-on-Chip (SoC) devices, more specifically the Xilinx Zynq UltraScale+ (ZUS+) family. While the application varies greatly, these devices are regularly used for performing board management tasks, making them a fundamental element in the correct operation of the board. The large number of hundreds of SoC devices creates significant challenges in their firmware deployment, maintenance, and accessibility. Even though U-Boot on ZUS+ devices supports network boot through the Preboot Execution Environment (PXE), the standard ZUS+ boot process contains application-specific information at earlier boot steps, particularly within the First Stage Bootloader (FSBL). This prevents the initialization of several devices from a universal image. Inspired by the PXE boot process on desktop PCs, this paper describes split boot, a novel boot method tailored to the specific needs of the ZUS+. All application-specific configuration is moved to a network storage device and automatically fetched during the boot process. We considered the entire process, from firmware and software development to binary distribution in a large-scale system. The developed method nicely integrates with the standard Xilinx development toolset workflow.

A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs

Soft real-time streaming applications often process input data that evoke varying workloads for their tasks. This may lead to high energy consumption or deadline misses in case their mapping onto a heterogeneous MPSoC target architecture is not adapted, e.g., when tasks with high execution times for the current input are assigned to resources of low computational power. To handle the vast variety of different input data, we propose to cluster data with similar execution characteristics into so-called data scenarios for which we determine specialized mappings by performing a scenario-aware design space exploration (DSE). A runtime manager (RTM) uses these mappings to adapt the execution of the running applications to their upcoming input by first identifying their best-suited scenarios. Subsequently, the RTM selects mappings considering their identified scenarios, which minimize the total number of deadline misses and the consumed energy. We embed the RTM into hybrid application mapping (HAM); ergo, performing time-consuming optimizations offline. In this article, we propose a novel data-scenario-aware HAM methodology that can cope with multiple applications and comprises two novel scenario-based mapping selection algorithms: Inter-Application Resource Mediation Mapping introduces barely any runtime overhead. Adaptive multi-app mapping selection is highly adaptive to changes in the application workload but imposes a small runtime overhead. Our HAM approach is fully automated and uses machine-learning techniques to learn the selection of suitable mappings from training data sequences at design time. Experiments on three differently complex target architectures show that our proposed approach consistently outperforms existing state-of-the-art solutions regarding the number of deadline misses and consumed energy.

On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures

The mapping of soft real-time applications onto a heterogeneous MPSoC target architecture is of high importance for meeting deadlines and minimizing secondary objectives like the consumed energy on the platform. In particular, for applications with input-dependent workload variation, hybrid application mapping (HAM) has crystallized itself as the state-of-the-art mapping approach that combines time-intensive design space exploration with lightweight run-time management. However, one general problem of HAM is that the explored mappings and models are highly specific to a certain target architecture. If the architecture is modified or changed (e.g., due to hardware upgrades, downgrades, or architectural degradation), the design-time optimization has to be repeated once again, which might take up to multiple weeks. As a remedy, this article proposes a twofold mapping transfer methodology that speeds up the design-time optimization for a novel or modified target architecture based on the knowledge we gained from the optimization for the original source architecture. First, we describe a greedy mapping transfer heuristic that provides feasible mappings for the new architecture in negligible optimization time. Second, we present a mapping refinement heuristic that improves these mappings even further while needing only a fraction of the optimization time of state-of-the-art approaches. As we show in the evaluation section, our approach can drastically speed up the convergence of the optimization for the novel architecture even if the sizes of the original and novel target architecture or the characteristics of the used resources differ significantly. Note that our approach assumes that the source and target architectures are both tile-based Network-on-Chip (NoC) meshes.

A Measurement-Based Message-Level Timing Prediction Approach for Data-Dependent SDFGs on Tile-Based Heterogeneous MPSoCs

Fast yet accurate performance and timing prediction of complex parallel data flow applications on multi-processor systems remains a very difficult discipline. The reason for it comes from the complexity of the data flow applications w.r.t. data dependent execution paths and the hardware platform with shared resources, like buses and memories. This combination may lead to complex timing interferences that are difficult to express in pure analytical or classical simulation-based approaches. In this work, we propose the combination of timing measurement and statistical simulation models for probabilistic timing and performance prediction of Synchronous Data Flow (SDF) applications on MPSoCs with shared memories. We exploit the separation of computation and communication in our SDF model of computation to set-up simulation-based performance prediction models following different abstraction approaches. We especially propose a message-level communication model driven by a data-dependent probabilistic execution phase timing model. We compare our work against measurement on two case-studies from the computer vision domain: a Sobel filter and a JPEG decoder. We show that the accuracy and execution time of our modeling and evaluation framework outperforms existing approaches and is suitable for a fast yet accurate design space exploration.

Workload assignment for global real-time scheduling on unrelated clustered platforms

Heterogeneous MPSoCs are being used more and more, from cellphones to critical embedded systems. Most of those systems offer heterogeneous sets of identical cores. In this paper, we propose new results on the global scheduling approach. We extend fundamental global scheduling results on unrelated processors to results on unrelated multicore platforms, a more realistic model. We introduce several methods to construct the workload assignment of tasks to cores taking advantage of this new model. Every studied result is optimal regarding schedulability, and all the proposed methods but one have a polynomial time complexity. Thanks to the model, the produced schedules have a limited degree of migrations. The benefits of the methods are demonstrated and compared using synthetic tasks sets. Practical limitations of the global scheduling approach on unrelated platforms are discussed, but we argue that it is still worth investigating considering modern MPSoCs.

An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor System

In recent years, Field Programmable Gate Array (FPGA) has different, and novel combinations of soft and hard cores embedded with accelerators in the same chip. At present, “Heterogeneous Multiprocessor System-on-Chip” technology meets the needs of the FPGA architecture as it not only consumes less space but also its design is implemented to enhance the performance resulting in decreased power consumption. However, traditional approaches can work within a limited range of values incurring high-power consumption, and they need substantial hardware resources involving complex procedures. In our proposed work, the combination of Graph Theory Estimator and Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) is introduced. The principle notion of this proposed scheme is to optimize the required area resources and power consumption of the overall architecture by exploring the design space in a minimal time. The architecture uses a less number of hardware resources with a better outcome. The performances such as the latency, power consumption, delay, area and data rate are achieved better than the traditional works, and it is also application-aware with a multitask system. While comparing the outcome with the conventional asymmetric heterogeneous MPSoC method, the new DSEBBO design exhibits the performance improvement of 26.87% in data rate, and 37.18% reduction in average power consumption and 63.61% reduction in delay analysis under various traffic scenarios.

A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCs

Consideration of an embedded system’s timing behavior and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. In this article we present an ESL framework for timing and power aware virtual system prototyping of heterogeneous MPSoCs consisting of software, custom hardware and 3rd party IP components. In virtual platform, previously only used for functional software verification, our proposed timed value streams enable a hierarchical and composable power model. Our proposed ESL framework supports the integration of a broad range of system-level timing and power models into virtual platform. Power and timing models can either be generated from a functional C/C++ description or include state-machine based power models to existing functional and timed virtual platform (black-box) components. Our timed value stream based power model supports the run-time analysis of different platform power management strategies with configurable temporal abstraction, supporting simulation speed and accuracy trade-offs. This work evaluates timing and power back-annotation and power state machine based approaches with timed value streams in two use-cases: An MP3 decoder, compared to a power-aware ISS and gate-level simulation, and an FPGA based many-core architecture against measurements. Finally, the simulation time overhead of the proposed stream based power model is analyzed and discussed.

Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding

In heterogeneous multicore systems, the memory subsystem plays a critical role, since most core-to-core communications are conducted through the main memory. Memory efficiency has a substantial impact on system performance. Although memory traffic from multimedia cores generally manifests high row-buffer locality, which is beneficial to memory efficiency, the locality is often lost as memory streams are forwarded through networks-on-chip (NoC). Previous studies have discussed the techniques that improve memory visibility to reveal scattered row-buffer hit opportunities to the memory scheduler. However, extending local memory visibility introduces little benefit after the locality has been severely diluted. As the alternative approach, preserving row-buffer locality in the NoC has not been well explored. What is worse, it remains to be studied how to perform network traffic scheduling with the awareness of both memory efficiency and quality-of-service (QoS). In this article, we propose a router design with embedded row-index caches to enable locality-aware packet forwarding. The proposed design requires minor modifications to existing router microarchitecture and can be easily implemented with priority arbiters to integrate QoS support. Extensive evaluations show that the proposed design achieves higher memory efficiency than prior memory-aware routers, in addition to providing QoS support. On basis of extant QoS-aware routers, locality-aware forwarding helps to increase row-buffer hits by 58.32% and reduce memory latency by 14.45% on average. It also introduces a net reduction in DRAM and NoC energy cost by 27.82%.

Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA

For heterogeneous multi-core architectures, efficient development of parallel software is paramount. Fast and accurate compiler technology is required in order to exploit their advantages and to optimise for multiple objectives, such as performance and power.The work at hand presents a heuristic and state-of-the-art Evolutionary Multi Objective Algorithm (EMOA) approach to tackle this problem. The performance and consistency of the population based heuristic TONPET and the indicator based EMOA are compared and thoroughly analysed. For the evaluation, both are integrated into the SLX tool suite. Representative benchmarks and three different MPSoC platforms are chosen for an in-depth realistic analysis. For smaller and medium sized solution spaces, TONPET outperforms the EMOA with 4.7% better Pareto fronts on average, while being 18 × faster in the worst case. In vast solution spaces, the EMOA consistently produces 3% better Pareto fronts on average but TONPET runs 88 × faster in the worst case. Furthermore, for comparison purposes, a full performance consistency analysis on EMOA conducted.

SDMPSoC: Software-Defined MPSoC for FPGAs

Nowadays, heterogeneous Multiprocessor Systems-on-Chip are often used for a wide variety of applications such as image and signal processing due to the high computational power. However, the programming and designing of such systems requires a high expertise in hardware as well as software. This is in contrast to a short time-to-market which is essential for the industry. As a result, a crucial software productivity gap emerges. This work presents SDMPSoC which is an automatic development environment for heterogeneous and FPGA-based MPSoCs. Based on an MPI program, a heterogeneous MPSoC for FPGAs consisting of an arbitrary number of MicroBlaze processors and hardware modules is generated. Each process of the MPI program is executed by a MicroBlaze processor or a hardware module which can be selected using constraints. Furthermore, every MicroBlaze processor can be optimized by hardware modules that executes application-specific operations. All hardware modules can be easily programmed in the MPI program and are synthesized using high-level synthesis. Functions of the MPI program can be selected by pragmas for hardware modules that are connected to a MicroBlaze processor. A process of the MPI program can be selected by constraints for a hardware module that is a PE without MicroBlaze processor. To evaluate the environment in terms of scalability, performance and area, several use cases have been implemented on a Xilinx Zynq SoC. The development phase and programming of heterogeneous MPSoCs are significantly simplified by the automatic development environment.

Minimizing temperature and energy of real-time applications with precedence constraints on heterogeneous MPSoC systems

Abstract The energy issue of real-time applications with precedence-constrained tasks on heterogeneous systems has been studied recently. With the strikingly increasing power density due to the soaring system integration level, severe thermal issues arise which can in turn further aggravate the energy issues due to the strong temperature/leakage dependency. Any optimization should be insufficient if such dependency is not properly addressed. However, the state-of-the-art approaches either treat leakage power as a constant, or only adopt the dynamic power consumption as the heuristic metric to conduct the optimization, both of which cannot fully explore the optimization room for the two issues. To this end, we design an energy/thermal aware task scheduling approach by taking both the thermal and energy factors into consideration. The optimization is conducted from two aspects: first balance the energy/thermal loads of processors by assigning tasks in an energy/thermal aware heuristic way, and that of tasks by the deduced task-level deadlines; then reduce the waiting time between parallel tasks that share the same successor task. Extensive experiments conducted on real-world applications show that, the proposed approach can reduce more temperature by up to about 12∘C (depending on the specific application and related parameters) while keeping a competitive energy consumption compared with the state-of-the-arts.

A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets

In modern heterogeneous MPSoCs, the management of shared memory resources is crucial in delivering end-to-end QoS. Previous frameworks have either focused on singular QoS targets or the allocation of partitionable resources among CPU applications at relatively slow timescales. However, heterogeneous MPSoCs typically require instant response from the memory system where most resources cannot be partitioned. Moreover, the health of different cores in a heterogeneous MPSoC is often measured by diverse performance objectives. In this work, we propose the Self-Aware Resource Allocation framework for heterogeneous MPSoCs. Priority-based adaptation allows cores to use different target performance and self-monitor their own intrinsic health. In response, the system allocates non-partitionable resources based on priorities. The proposed framework meets a diverse range of QoS demands from heterogeneous cores. Moreover, we present a runtime scheme to configure priority-based adaptation so that distinct sensitivities of heterogeneous QoS targets with respect to memory allocation can be accommodated. In addition, the priority of best-effort cores can also be regulated.

Parallel Applications Mapping onto Network on Chip Based on Heterogeneous MPSoCs Using Hybrid Algorithms

Mapping parallel applications onto a network on chip (NoC) that is based on heterogeneous MPSoCs is considered as an instance of an NP-hard and a multi-objective problem. Various multi-objective algorithms have been proposed in the literature to handle this issue. Metaheuristics stand out as highly appropriate approaches to deal with this kind of problem. These metaheuristics are classified into two sets: population-based metaheuristics and single solution-based ones. To take advantage of the both sets, the trend is to use hybrid solutions that have shown to give better results. In this article, the authors propose to hybridize these two metaheuristics sets to find good Pareto mapping solutions to optimize the execution time and the energy consumption simultaneously. The experimental results have shown that the proposed hybrid algorithms give high quality non-dominated mapping solutions in a reasonable runtime.

A meta heuristic-based task scheduling and mapping method to optimize main design challenges of heterogeneous multiprocessor embedded systems

In this paper, we proposed a meta heuristic-based task scheduling method to optimize lifetime reliability, performance and power consumption of heterogeneous MPSoCs. Lifetime reliability is affected by several failure mechanisms with different behaviors which are mainly dependent on temperature and its variation pattern. To improve lifetime reliability of multiprocessor systems, it is required to consider the effect of all potential failures and their distinct impact during the optimization process. Moreover, improving power consumption and execution time makes the optimization process more complicated due to the existing trade offs among these parameters. Our proposed task scheduling method optimizes lifetime reliability by considering the effect of all failure mechanisms, power consumption and execution time of heterogeneous MPSoCs. It employs a design space exploration engine based on the Non-dominated Sorting Genetic Algorithm (NSGA-II) to make the exploration process more efficient. To demonstrate the effectiveness of our proposed task scheduling and mapping method and compare it to the related studies, several experiments are performed. Moreover, the importance of thermal cycling (TC), as an emerging thermal concern in computing the lifetime reliability of MPSoCs, and also the capability of our proposed method in controlling it are studied and compared to related research. Experimental results show that employing our proposed scheduling method improves performance, lifetime reliability and power consumption about 24%, 30% and 3.6% respectively on average compared to two selected related studies. Furthermore, our proposed approach decreases the occurrence rate of all failure mechanisms compared to related studies and outperforms them in term of the thermal cycling rate about 48% on average.

A temperature-aware and energy-efficient fuzzy technique to schedule tasks in heterogeneous MPSoC systems

Energy consumption and elevating the chip temperature become a serious challenge in designing embedded systems mainly due to transistor scaling and integration of more components into a single chip. The temperature of the chip has significant effects on leakage current, energy consumption and reliability of the chip; hence, discovering a mechanism that reduces both energy consumption and temperature of the chip is of utmost significance. An effective task scheduling in a real-time multiprocessor system-on-chip system has a direct impact on energy consumption and temperature of the chip. Several task scheduling and task assignment techniques have been proposed to achieve this goal. Most of those works consider only utilization of processors to distribute tasks among processors in order to reduce energy consumption. Meanwhile, those works try to reduce temperature in the step of task scheduling, separately in each processor. This paper proposes a fuzzy-based technique to distribute real-time tasks among processors in order to reduce both temperature and energy consumption simultaneously. Simulation results show that our proposed technique is more efficient in terms of reducing the energy consumption compared to a well-known state-of-the-art method (up to 9%) while offering a more balanced and moderate temperatures for processors and hindering hot spot.

Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators

This work proposes three different methods to automatically characterize heterogeneous MPSoCs composed of a variable number of masters (in the form of processors) and hardware accelerators (HWaccs). These hardware accelerators are given as Behavioral IPs (BIPs) mapped as loosely coupled accelerators on a shared bus system (i.e. AHB, AXI). BIPs have a distinct advantage over traditional RT-level based IPs given VHDL or Verilog: The ability to generate micro-architectures with different area vs. performance trade-offs from the same description. This is usually done by specifying different synthesis directives in the form of pragmas. This in turn implies that using different mixes of the accelerators’ micro-architectures lead to SoCs with unique area vs. performance trade-offs.Two of the three methods proposed are based on cycle-accurate simulations of the complete MPSoC, while the third method accelerates this exploration by performing it on a Configurable SoC FPGA. Extensive experimental results compare these three methods and highlight their strengths and weaknesses.

Design and Implementation of Shared Bus based Heterogeneous MPSoC

Design and Implementation of Shared Bus based Heterogeneous MPSoC

Cost-Constrained QoS Optimization for Approximate Computation Real-Time Tasks in Heterogeneous MPSoCs

Internet of Things devices, such as video-based detectors or road side units are being deployed in emerging applications like sustainable and intelligent transportation systems. Oftentimes, stringent operation and energy cost constraints are exerted on this type of applications, necessitating a hybrid supply of renewable and grid energy. The key issue of a cost-constrained hybrid of renewable and grid power is its uncertainty in energy availability. The characteristic of approximate computation that accepts an approximate result when energy is limited and executes more computations yielding better results if more energy is available, can be exploited to intelligently handle the uncertainty. In this paper, we first propose an energy-adaptive task allocation scheme that optimally assigns real-time approximate-computation tasks to individual processors and subsequently enables a matching of the cost-constrained hybrid supply of energy with the energy demand of the resultant task schedule. We then present a quality of service (QoS)-driven task scheduling scheme that determines the optional execution cycles of tasks on individual processors for optimization of system QoS. A dynamic task scheduling scheme is also designed to adapt at runtime the task execution to the varying amount of the available energy. Simulation results show that our schemes can reduce system energy consumption by up to 29% and improve system QoS by up to 108% as compared to benchmarking algorithms.