A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCs

Abstract

Consideration of an embedded system’s timing behavior and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. In this article we present an ESL framework for timing and power aware virtual system prototyping of heterogeneous MPSoCs consisting of software, custom hardware and 3rd party IP components. In virtual platform, previously only used for functional software verification, our proposed timed value streams enable a hierarchical and composable power model. Our proposed ESL framework supports the integration of a broad range of system-level timing and power models into virtual platform. Power and timing models can either be generated from a functional C/C++ description or include state-machine based power models to existing functional and timed virtual platform (black-box) components. Our timed value stream based power model supports the run-time analysis of different platform power management strategies with configurable temporal abstraction, supporting simulation speed and accuracy trade-offs. This work evaluates timing and power back-annotation and power state machine based approaches with timed value streams in two use-cases: An MP3 decoder, compared to a power-aware ISS and gate-level simulation, and an FPGA based many-core architecture against measurements. Finally, the simulation time overhead of the proposed stream based power model is analyzed and discussed.