Heterogeneous Integration Process Research Articles

Heterogeneous micro-architectonic integration of SU-8 and highly entangled polyacrylamide hydrogel to realize cut-resistant soft superhydrophobic surfaces

This paper presents a novel idea to create cut-resistant superhydrophobic (SHPo) surfaces by integrating an array of SU-8 micropillars on a highly entangled polyacrylamide (PAAm) hydrogel substrate. We begin by demonstrating that this highly entangled PAAm hydrogel exhibits superior resistance to cutting while being as transparent, flexible, and stretchable as other polymeric substrates like polydimethylsiloxane (PDMS). Currently, there are no well-known methods or chemicals to directly integrate SU-8 and PAAm with a covalent bond. To overcome this challenge, we introduce a thin layer of chemically modified PDMS between the SU-8 and PAAm so that covalent bonds can be formed between both the SU-8/PDMS interface and the PDMS/PAAm interface. After validating the reliability of the bonding in our experiments, we develop a heterogeneous integration process to fabricate the desired SHPo surface. To demonstrate the critical role of PAAm hydrogel in achieving the cut-resistant SHPo surface, we contrast this new SHPo surface with a reference version that uses a PDMS substrate instead. We conduct microscopic inspections using scanning electron microscopy (SEM) and a contact angle goniometer before and after cutting the two surfaces. These evaluations show significant differences in their structural integrity and behavior in water interaction.

Optimizing MMIC performance: The synergy of AI models and heterogeneous integration process

AbstractThis study presents a novel approach for optimizing the parameters of monolithic microwave integrated circuit (MMIC) functional units using machine‐learning techniques and multi‐objective optimization algorithms. We utilize advanced machine‐learning methods, including random forest, artificial neural networks (ANNs), and recurrent neural networks (RNNs), to construct highly accurate models that predict the performance of these units. These models are subsequently integrated with a multi‐objective optimization algorithm, specifically the multi‐objective particle swarm optimization (MOPSO), to generate inverse design solutions for both the geometric designs of the units and the fabrication parameters of the heterogeneous integration process. Our approach, which has been validated through chip fabrication and testing, has demonstrated its robustness as a tool for achieving optimal MMIC designs. It not only reduces the design time but also enhances the manufacturability of MMICs, thereby opening new avenues in microwave and RF circuit design.

Miniaturised wideband bandpass filter with good selectivity based on 3D heterogeneous integrated passive device technology

AbstractThe miniaturised wideband filter with good frequency selectivity and wide stopband is proposed, which is based on three‐dimensional (3D) heterogeneous integrated passive device technology. The proposed sixth‐order wideband bandpass filter is based on the magnetic‐coupling‐loaded highpass‐lowpass lumped topology and implemented by the 3D heterogeneous integration process, integrating GaAs‐based and Glass‐based micro‐nano‐scale processes together. Then, lumped inductors are designed in the Glass substrate with low dielectric loss tangent and realised by a three‐dimensional spiral structure. Therefore, the inductors have high quality factors and small sizes. The lumped capacitors are designed using the GaAs thin film process. Finally, a prototype with a 3‐dB fractional bandwidth of 42% is designed and fabricated at 3.875 GHz (f0). The upper‐stopband attenuation higher than 30 dB is extended to more than 5.15f0. It occupies only 0.014 × 0.018 λ02 (1.1 × 1.42 mm2), where λ0 is the free‐space wavelength at f0.

Economic integration of temporary and permanent migrants: Between migrant and return migrant status

This article examines the economic integration and reintegration outcomes and processes of temporary and permanent migrants in the case of rural-to-urban migrants in China. Using a life-course perspective, I measure the integration levels of both temporary and permanent migrants in urban destinations and rural hometowns over time. Through this measurement, I investigate the differences between temporary and permanent migrants in terms of economic integration in urban destinations and reintegration in rural hometowns. The findings suggest that temporary migrants experience lower economic integration and reintegration levels than permanent migrants, highlighting the persistent advantages of permanent migrants over time. Additionally, I explore and compare the underlying processes that explain this gap for temporary and permanent migrants in both urban destinations and rural hometowns over time, including the selection process and the heterogeneous integration process. The results indicate that permanent migrants are consistently more educated than temporary migrants, reflecting a consistently positive selection of permanent migrants. Furthermore, temporary migrants rely more on individual traits, such as gender and marital status, than permanent migrants for integration and reintegration. By considering both the integration and reintegration of temporary and permanent migrants, this study provides a holistic and dynamic understanding of their integration outcomes and processes. The underlying mechanisms, the theoretical contributions of these mechanisms, and the implications of these findings to a broader migration context are also discussed.

Heterogeneous integration of Si photodiodes on silicon nitride for near-visible light detection.

Silicon nitride (SiN) is used extensively to complement the standard silicon photonics portfolio. However, thus far demonstrated light sources and detectors on SiN have predominantly focused on telecommunication wavelengths. Yet, to unlock the full potential of SiN, integrated photodetectors for wavelengths below 850 nm are essential to serve applications such as biosensing, imaging, and quantum photonics. Here, we report the first, to the best of our knowledge, microtransfer printed Si p-i-n photodiodes on a commercially available SiN platform to target wavelengths <850 nm. A novel heterogeneous integration process flow was developed to offer a high microtransfer printing yield. Moreover, these devices are fabricated with CMOS compatible and wafer-scale technology.

Wafer-Scale Si–GaN Monolithic Integrated E-Mode Cascode FET Realized by Transfer Printing and Self-Aligned Etching Technology

In this article, Si (100) inks’ array is integrated on SiN/AlGaN/GaN substrate to demonstrate a zero deviation and wafer-scale Si–GaN monolithic integration by transfer printing and self-aligned etching technology. During the heterogeneous integration process, it does not depend on any equipment, such as metal–organic chemical vapor deposition (MOCVD) (epitaxial growth) and wafer bonding machine (wafer bonding) which are costly. The transferred Si and SiN/AlGaN/GaN substrates show an excellent interface morphology. Based on this material system, the monolithic integrated E-mode cascode FETs are demonstrated with good uniformity. The ${I}_{GS}$ is below 10−5 mA/mm within a large gate voltage swing of ±18 V. Threshold voltages of a series of cascode FETs are extracted as 2.2 V (±0.2 V). This novel low-cost technology shows great potential in monolithic heterogeneous integration.

CMOS Compatible High‐Performance Nanolasing Based on Perovskite–SiN Hybrid Integration

AbstractCoherent light sources in silicon photonics are the long‐sought Holy Grail because silicon‐based materials have indirect bandgap. Traditional strategies for realizing such sources, e.g., heterogeneous photonic integration, strain engineering, and nonlinear process, are technologically demanding. Here, a hybrid lasing device composed of perovskite nanocrystals and silicon nitride nanobeam cavity is demonstrated. SiN photonic crystal naonobeam cavities are fabricated on a solid substrate with significantly improved thermal and mechanical stabilities compared to conventional suspended ones. In addition, adding a poly (methyl methacrylate) (PMMA)‐encapsulation layer on top of the SiN can significantly boost the Q‐factor of the cavity mode. By dispersing perovskite nanocrystals as emitters in the PMMA layer, high‐performance coherent emissions are obtained in terms of lasing threshold, linewidth, and mode volumes. The work offers a compelling way of creating solution‐processed active integrated photonic devices based on the mature platform of silicon photonics for applications in optical information science and photonic quantum technology.

A multifunctional standardized magnetic tunnel junction stack embedding sensor, memory and oscillator functionality

The objective of this study is to co-integrate multiple digital and analog functions together within CMOS by developing a universal magnetic tunneling junction stack (MTJ) capable of realizing logic, memory, and analog functions, within a single baseline technology. This will allow monolithic heterogeneous integration, fast and low-power processing, and high integration density, particularly useful for Internet of Things (IoT) platforms. This unique spintransfer-torque (STT) MTJ is called Multifunctional Standardized Stack (MSS). This paper presents the progress regarding memory, oscillator and sensor functionalities targeted for the technology. We show that a single magnetic stack deposition can be used to obtain these three functionalities on the same wafer.

A Heterogeneous Integrated MEMS Inertial Switch With Compliant Cantilevers Fixed Electrode and Electrostatic Locking to Realize Stable On-State

A novel heterogeneous integrated inertial micro-switch has been designed with adjustable acceleration threshold and a stable ‘on’-state due to a predefined bias voltage. The bias voltage is applied onto the large-area parallel-plate electrodes, which endows the movable proof-mass with electrostatic forces. With an external excitation acceleration, the movable electrode moves to the fixed electrode and it can be locked by the electrostatic force onto the compliant electrical contacts, which are composed of micro-cantilever array to eliminate the contact rebound during electrostatic pull-in process. Both the dynamic response of the proof-mass and the relationship between the bias voltage and the inertial excitation acceleration were analyzed using theoretical model and finite element simulation. A unique heterogeneous integration process including both the silicon-based and non-silicon surface micromachining processes was adopted to fabricate the switch. The tests using a standard dropping hammer system demonstrated that the switch could keep a stable switch-on at the 57 g excitation acceleration and 38 V bias voltage. As wide as 52% adjustment range of the acceleration threshold was obtained when the applied bias voltage was from 38 V to 44 V. The tested relationship between the bias voltage and the external acceleration was very consistent with the simulated relationship. [2019-0038]

Physics of self-aligned assembly at room temperature

Self-aligned assembly, making use of capillary forces, is considered as an alternative to active alignment during thermo-compression bonding of Si chips in the 3D heterogeneous integration process. Various process parameters affect the alignment accuracy of the chip over the patterned binding site on a substrate/carrier wafer. This paper discusses the chip motion due to wetting and capillary force using a transient coupled physics model for the two regimes (that is, wetting regime and damped oscillatory regime) in the temporal domain. Using the transient model, the effect of the volume of the liquid and the placement accuracy of the chip on the alignment force is studied. The capillary time (that is, the time it takes for the chip to reach its mean position) for the chip is directly proportional to the placement offset and inversely proportional to the viscosity. The time constant of the harmonic oscillations is directly proportional to the gap between the chips due to the volume of the fluid. The predicted behavior from transient simulations is next experimentally validated and it is confirmed that the liquid volume and the initial placement affect the final alignment accuracy of the top chip on the bottom substrate. With statistical experimental data, we demonstrate an alignment accuracy reaching &amp;lt;1 μm.

(Invited) Diverse Accessible Heterogeneous Integration (DAHI) Foundry at Northrop Grumman Aerospace Systems (NGAS)

The requirements for future systems are increasingly demanding not only form the point of view of performance, but also from size, weight, power and cost (SWAP-C) considerations. This translates into the need for advanced integration of additional complexity and performance of electronic functions into smaller areas and volumes. In addition, to enable higher performance of the microelectronic technology in which these functions are implemented, it is not enough to use one single semiconductor technology but to combine or integrate several high performance technologies in an efficient and cost effective way. In most cases this involves the integration of semiconductor technologies based on different substrates or different technology nodes based on the same substrate. The combination of two or more dissimilar microelectronic technologies, or heterogeneous integration, leads to significant higher design flexibility and capability. The more adaptable and more intimate is this heterogeneous integration between two or more technologies, the more flexibility is given to the designer for the selection of the technology for a specific function, or even better, for an optimum combination of different transistor technologies in the same function or cell in the design. Northrop Grumman Aerospace Systems (NGAS) under the Diverse Accessible Heterojunction Integration (DAHI) DARPA program is developing heterogeneous integration processes, design kits and thermal simulation tools to integrate submicron CMOS, InP HBT, GaN HEMT and high-Q passive technologies for advanced DoD and other government systems. We have demonstrated integration of NGAS’ TF4 and TF5 InP HBT and GaN20 GaN on SiC HEMT technologies on IBM’s 65nm CMOS and GlobalFoundries’ (GFUS) 45nm CMOS (12SOI). The NGAS DAHI integration process has several advantages. It is scalable to 200 mm and 300 mm CMOS wafers and fully compatible with all Si technologies. All the technologies to be integrated are independently fabricated in parallel for optimum cycle time and decoupled line yield. The NGAS DAHI integration approach also offers advantages from the thermal management point of view. The low thermal resistance heterogeneous interconnects (HICs) enable flexible electrical and thermal routing. The GaN HEMT is integrated with its backside facing the CMOS front side to allow better intra-chip heat spreading and large inter-chip HIC heat sink arrays. The thickness of the Silicon Carbide (SiC) substrate in the GaN HEMT chiplet is designed to be thick enough to allow optimum lateral heat spreading before reaching the thermal HIC interface. The TF InP HBT technology is integrated with its front side facing the CMOS front side for maximum density of interconnects. An additional important task in the development of the DAHI technology is the creation of an integrated DAHI process design kit (PDK). The objective of the DAHI PDK development is to have a flexible design environment that can accommodate schematics, layouts and simulations of integrated DAHI circuits with device-level integration designs of a wide variety of technologies. Integration circuit results will be presented at the conference. Acknowledgements This work is supported by DARPA DAHI Program under AFRL contract No. FA8650-13-C-7312, Daniel Green DARPA program manager and Robert Fitch AFRL COTR. The views expressed are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government.

Adhesive wafer bonding with ultra-thin intermediate polymer layers

Wafer bonding methods with ultra-thin intermediate bonding layers are critically important in heterogeneous 3D integration technologies for many NEMS and photonic device applications. A promising wafer bonding approach for 3D integration is adhesive bonding. So far however, adhesive bonding processes relied on relatively thick intermediate adhesive layers. In this paper, we present an adhesive wafer bonding process using an ultra-thin intermediate adhesive layer with sub-200nm thickness. We demonstrate adhesive bonding of silicon wafers with a near perfect bonding yield of >99% and achieve less than ±10% non-uniformity of the intermediate layer thickness across an entire 100 mm-diameter wafer. A bond strength of 4.8MPa was measured for our polymer adhesive, which is considerably higher than previously reported for other ultra-thin film adhesives. Additionally, the adhesive polymer used in the proposed method features excellent chemical and mechanical stability. We also report on a potential strategy for mitigating the formation of micro-voids in the polymer adhesive at the bond interface. Furthermore, the polymer adhesive can be sacrificially removed by oxygen plasma etching for both isotropic and anisotropic release etching. The characteristics of the adhesive wafer bonding process and its compatibility with CMOS wafers, makes it very attractive for heterogeneous 3D integration processes targeted at CMOS-integrated NEMS and photonic devices.

A Revolution on the Horizon from DARPA: Heterogeneous Integration for Revolutionary Microwave\/Millimeter-Wave Circuits at DARPA: Progress and Future Directions

The Microsystems Technology Office of the U.S. Defense Advanced Research Projects Agency (DARPA) is developing revolutionary materials, devices, and integration techniques to meet the performance requirements for advanced microwave and millimeter-wave (mmW) systems. The DARPA Compound Semiconductor Materials on Silicon (COSMOS) program focused on developing new methods to tightly integrate compound semiconductor (CS) technologies within state-of-the-art silicon (Si) complementary?metal-oxide-semiconductor (CMOS) circuits to achieve unprecedented circuit performance levels. The DARPA Diverse Accessible Heterogeneous Integration (DAHI) program is continuing that work by developing heterogeneous integration processes to intimately combine advanced CS devices, as well as other emerging materials and devices, with high-density Si CMOS technology. DARPA has also pushed limits in Si technology and driven seminal developments in gallium nitride (GaN) device technology. Taken together, these programs are addressing many critical challenges for next-generation microwave and mmW systems and seek to revolutionize U.S. Department of Defense (DoD) capabilities in these areas.

A Review of Electronic-Photonic Heterogeneous Integration at DARPA

The Defense Advanced Research Projects Agency (DARPA) has developed programs in integrated photonics for over a decade. From the Electronic-photonic Integrated Circuits (EPIC) program to the more recent Electronic-photonic Heterogeneous Integration (E-PHI) program, DARPA programs have established a library of high-performance silicon photonic devices and have demonstrated heterogeneous integration processes. These components and integration techniques, combined with automated design software tools, form the basis of the new American Institute for Manufacturing Integrated Photonics which will establish a photonics manufacturing ecosystem in the United States through a combination of public and private funds.

(Invited) Diverse Accessible Heterogeneous Integration (DAHI) Foundry at Northrop Grumman Aerospace Systems (NGAS)

The requirements for future systems are increasingly demanding not only form the point of view of performance, but also from size, weight, power and cost (SWAP-C) considerations. This translates into the need for advanced integration of additional complexity and performance of electronic functions into smaller areas and volumes. In addition, to enable higher performance of the microelectronic technology in which these functions are implemented, it is not enough to use one single semiconductor technology but to combine or integrate several high performance technologies in an efficient and cost effective way. In most cases this involves the integration of semiconductor technologies based on different substrates. The combination of two or more dissimilar microelectronic technologies, or heterogeneous integration, leads to significant higher design flexibility and capability.The more adaptable and more intimate is this heterogeneous integration between two or more technologies, the more flexibility is given to the designer for the selection of the technology for a specific function, or even better, for an optimum combination of different transistor technologies in the same function or cell in the design. Northrop Grumman Aerospace Systems (NGAS) under the Diverse Accessible Heterojunction Integration (DAHI) DARPA program is developing heterogeneous integration processes, design kits and thermal simulation tools to integrate submicron CMOS, InP HBT, GaN HEMT and high-Q passive technologies for advanced DoD and other government systems. We have demonstrated integration of NGAS’ TF4 and TF5 InP HBT and GaN20 GaN on SiC HEMT technologies on IBM’s 65nm CMOS and GlobalFoundries’ 45nm SOI. The NGAS DAHI integration process has several advantages. It is scalable to 200 mm and 300 mm CMOS wafers and fully compatible with all Si technologies. All the technologies to be integrated are independently fabricated in parallel for optimum cycle time and decoupled line yield. The NGAS DAHI integration approach also offers advantages from the thermal management point of view. The low thermal resistance heterogeneous interconnects (HICs) enable flexible electrical and thermal routing. The GaN HEMT is integrated with its backside facing the CMOS front side to allow better intra-chip heat spreading and large inter-chip HIC heat sink arrays. The thickness of the Silicon Carbide (SiC) substrate in the GaN HEMT chiplet is designed to be thick enough to allow optimum lateral heat spreading before reaching the thermal HIC interface. The TF InP HBT technology is integrated with its front side facing the CMOS front side for maximum density of interconnects. An additional very important task in the development of the DAHI technology is the creation of an integrated DAHI process design kit (PDK). The objective of the DAHI PDK development is to have a flexible design environment that can accommodate schematics, layouts and simulations of integrated DAHI circuits with device-level integration designs of a wide variety of technologies. Integration circuit results will be presented at the conference.

A Stream Processing System for Multisource Heterogeneous Sensor Data

With the rapid development of the Internet of Things (IoT), a variety of sensor data are generated around everyone’s life. New research perspective regarding the streaming sensor data processing of the IoT has been raised as a hot research topic that is precisely the theme of this paper. Our study serves to provide guidance regarding the practical aspects of the IoT. Such guidance is rarely mentioned in the current research in which the focus has been more on theory and less on issues describing how to set up a practical system. In our study, we employ numerous open source projects to establish a distributed real time system to process streaming data of the IoT. Two urgent issues have been solved in our study that are (1) multisource heterogeneous sensor data integration and (2) processing streaming sensor data in real time manner with low latency. Furthermore, we set up a real time system to process streaming heterogeneous sensor data from multiple sources with low latency. Our tests are performed using field test data derived from environmental monitoring sensor data collected from indoor environment for system validation. The results show that our proposed system is valid and efficient for multisource heterogeneous sensor data integration and streaming data processing in real time manner.

Scaling of three-dimensional interconnect technology incorporating low temperature bonds to pitches of 10 µm for infrared focal plane array applications

This paper focuses on the application of low temperature bonding to the fabrication of three-dimensional (3D) massively parallel signal processors for high performance infrared imagers. We review two generations of the 3D heterogeneous integration process. The first generation process, compatible with pixel sizes in the 20 to 30 µm range, relies on low temperature epoxy bonding that is followed by the formation of copper-filled through-silicon vias (TSVs). The second generation process, scalable to pixel sizes of 10 µm and smaller, employs solid–liquid diffusion bonding of copper–tin to copper at 250 °C; the bonding follows TSV fabrication. To demonstrate the second generation process, we fabricated 3D test vehicles in the form of 640 × 512 arrays of vertical interconnects composed of TSVs and metal–metal bonds on a 10 µm pitch. We characterized electrical conductivity of the interconnects, the isolation resistance between the interconnects, and the operability and yield of the arrays. The successful demonstration of the interconnect technology paves the way to a functional demonstration of 3D signal processors in infrared imagers with 10 µm pixels.

InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With &gt; 70-dB SFDR

A prototype 13-b 1.33-Gsps digital-to-analog converter (DAC) implemented in a unique heterogeneous integration process (combining 0.45-μm InP HBT with 0.18-μm CMOS) is presented. Measured performance of greater than 70 dB SFDR is achieved across a 500-MHz bandwidth centered at 1 GHz (second Nyquist band). Heterogeneous integration enables each circuit element to be implemented in the transistor technology best suited to the circuit function. Low dc power is achieved by implementing the digital front-end in a standard silicon CMOS technology, while InP HBT technology is used to implement the high-speed/high-precision current-steering DAC core. The core DAC employs a segmented architecture with three unary most significant bits and an R-2R ladder for the ten least significant bits. No calibration circuitry is required to achieve better than 11 b of dc linearity. Dynamic performance is enhanced by employing an ultra-high-linearity return-to-zero (RZ) analog output deglitcher switch. Measured performance data for three different circuit design variations of the output switch (incorporating a varying mix of CMOS and InP HBT devices) is presented.

(Invited) Nanoscale Heterogeneous Reactions and Interfaces in Ge/Si and for III-V on Si Integrated Devices

In the pursuit of realizing sub-10 nm transistor channel lengths in homogenous and heterostructured materials, nanoscale defects and hetero-interfaces can significantly impact the formation of alloyed metal contacts conventionally used in CMOS devices. We utilize in-situ transmission electron microscopy to unveil new observations on the detailed formation of such alloys and interfaces at an atomic scale by capturing single nucleation events during the reaction of Ni with Si, Ge and Ge/Si core/shell nanowires and assess their resultant transistor performance. We then utilized the NiSi reaction to develop a novel heterogeneous integration process for III-V semiconductors on planar and patterned Ni electrodes in a fab-compatible process. We demonstrate the operation of the first InGaAs FinFETs on Si.

III-V-on-silicon multi-frequency lasers

Compact multi-frequency lasers are realized by combining III-V based optical amplifiers with silicon waveguide optical demultiplexers using a heterogeneous integration process based on adhesive wafer bonding. Both devices using arrayed waveguide grating routers as well as devices using ring resonators as the demultiplexer showed lasing with threshold currents between 30 and 40 mA and output powers in the order of a few mW. Laser operation up to 60°C is demonstrated. The small bending radius allowable for the silicon waveguides results in a short cavity length, ensuring stable lasing in a single longitudinal mode, even with relaxed values for the intra-cavity filter bandwidths.