Hardware Redundancy Research Articles

Модульные коды с суммированием в системах функционального контроля. II. Уменьшение структурной избыточности систем функционального контроля

Модульные коды с суммированием в системах функционального контроля. II. Уменьшение структурной избыточности систем функционального контроля

Development of High-Availability ATCA/PCIe Data Acquisition Instrumentation

Latest Fusion energy experiments envisage a quasi-continuous operation regime. In consequence, the largest experimental devices, currently in development, specify high-availability (HA) requirements for the whole plant infrastructure. Highly available systems operate seamlessly in the case of component failure, ensuring safety of equipment, people, environment and investment. Control and Data Acquisition (C&DA) systems for Fusion diagnostics are considered mission-critical and require high degrees of availability. IPFN developed a C&DA system for fast control of advanced Fusion devices, targeting HA. The hardware platform is based on in-house developed Advanced Telecommunication Computing Architecture (ATCA) instrumentation modules–digitizing and data switch blades using PCI Express (PCIe) over the ATCA backplane Fabric Channel Interface, connecting to an external PCIe host computer. At the hardware management level, the system architecture takes advantage of ATCA’s HA characteristics, such as its redundant hardware components, redundant backplane topologies and Field Replaceable Unit (FRU) “Hot Swap”. At the software level, PCIe supports “Hot Plug” graceful device insertion and removal. The implementation of PCIe Hot Plug for the ATCA form-factor is one of the major tasks involved and a solution for such implementation was also developed. The paper describes how IPFN C&DA system can be setup to take advantage of both ATCA and PCIe features to perform with the desired degree of availability, by implementing fail-over mechanisms based on the use of redundancy, thus being suitable for advanced C&DA systems in Fusion.

Ways to set up a concurrent error detection system for logical circuits without memory

Classical and modulo codes with summation of active bits of data vectors are often used to set up a concurrent error detection system for logical circuits without memory. Due to specificity in code generation, the number of ways for organizing the concurrent error detection system is equal to the number of inputs of the tested object. The task of expending the set of codes with summation has appeared. Methods of digital device theory, coding theory, and technical diagnostic theory are used for solving this problem. The generalized algorithm for generating the generic class of modulo modified code with summing of the active bits of data vectors is presented and the set’s cardinality is determined for the given number of outputs of the tested object. The essence of the presented class of codes lies in the determination of the smallest nonnegative deductions of a data vector’s weight and correction of the obtained modified weights. Modulo modified codes with summing of the active bits of data vectors are characterized by different properties of error detection in functional diagnostic systems. This makes it possible to generate dependable digital devices with reduced hardware redundancy and power consumption.

Traffic demand-aware topology control for enhanced energy-efficiency of cellular networks

The service provided by mobile networks operated today is not adapted to spatio-temporal fluctuations in traffic demand, although such fluctuations offer opportunities for energy savings. In particular, significant gains in energy efficiency are realizable by disengaging temporarily redundant hardware components of base stations. We therefore propose a novel optimization framework that considers both the load-dependent energy radiated by the antennas and the remaining forms of energy needed for operating the base stations. The objective is to reduce the energy consumption of mobile networks, while ensuring that the data rate requirements of the users are met throughout the coverage area. Building upon sparse optimization techniques, we develop a majorization-minimization algorithm with the ability to identify energy-efficient network configurations. The iterative algorithm is load-aware, has low computational complexity, and can be implemented in an online fashion to exploit load fluctuations on a short time scale. Simulations show that the algorithm can find network configurations with the energy consumption similar to that obtained with global optimization tools, which cannot be applied to real large networks. Although we consider only one currently deployed cellular technology, the optimization framework is general, potentially applicable to a large class of access technologies.

RSVP – Software Implemented Fault Tolerant Computing

This paper aims to describe a low cost technique for gaining software implemented fault tolerance without using design diversity-based N versions redundancy in both software and hardware. The proposed approach uses a robust single-version programming (RSVP) scheme for an application that executes on a single machine. RSVP employs triplicate application programme along with multistage voting at inputs and outputs to tolerate single-point operational faults in input data, output data, an individual processing module and in an individual voting module through error masking. It is not aimed to tolerate software design bugs. This is a useful tool for designing a robust low-cost computing application.

FPGA implementation of area-efficient single precision floating point complex divider with fault detection

Despite the applications of complex division in many fields like signal processing, control theory, telecommunication, etc., complex division algorithms are often treated with least importance. Most of the complex division modules are to be used in environments where fault-tolerance is required. FPGA is considered as a major candidate to implement such computationally intensive tasks because of its inherent properties. Interconnect faults and logic faults are two of the major types of faults likely to occur in FPGAs. Most of the existing works on fault-tolerant complex division uses hardware redundancy technique. This work proposes a technique to implement a complex division module with fault detection capability on FPGA. A module reuse technique is used to make the architecture area-efficient. The operands are being represented in 32-bit single precision floating point format.

Study of a Computer-Based Control System with Fault-Tolerant and Fail-Safe Behavior

Abstract The software and hardware of Safety Critical Systems - SCS, which control special critical technology process or operation, are subject of enhanced requirements for reliability and inadmissibility of any incorrect controlling influences (safety) after failures. This paper suggests and investigates a hybrid computerbased fail-safe/fault-tolerance FST-structure with single reservation, which has the qualities to meet these requirements. The base system 2 ∨ 2, based on which it is built, is studied in the previous edition of Information Technjlogies and Control. For derivation of probabilistic models through which to establish the efficiency of the strutucral redundancy in a fault-tolerant structure, in this paper are used the published results. Formulas are derived for the probability of failure-free operation (availability coefficient), for safe failure and for unidentified (dangerous) failure. Models are found for calculation of the enhancement of reliability and the variation of safety relative to the base system 2 ∨ 2. Subject of analysis are type software and hardware modifications of the proposed general scheme used in the practice of different companies, which manufacture and operate SCSs. It is proven that at the expense of acceptable hardware redundancy and insignificant increase of dangerous failures the probability of interruption of the operation of the FST- system and its down-time due to failure may decrease by tenths of thousands of times.

A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder

This paper presents a Viterbi-specific 2T gain cell- based embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.

Can Algorithm Diversity in Stream Cipher Implementation Thwart (Natural and) Malicious Faults?

Hardware implementations of stream and other ciphers are vulnerable to natural faults. Moreover, attackers can launch fault attacks on these implementations. Concurrent error detection is used as a countermeasure against natural and malicious faults. We propose an algorithm diversity (AD) to detect natural and malicious faults in stream ciphers. We compare AD with hardware, time, and information redundancies. Hardware redundancy has 100% hardware overhead, but is not secure against fault attacks. Time redundancy has lower hardware overhead, but is vulnerable to faults that are injected in both the computation and recomputation. Information redundancy techniques, such as parity, cannot detect an even number of faulty bits. Information redundancy techniques, such as robust code, have higher fault miss rate (FMR) with higher hardware overhead. If robust code is configured to have lower FMR than AD in certain attacker model, the hardware overhead is excessively high. AD provides higher security compared to existing techniques. It enables a cost-effective tradeoff between security, performance overhead, and hardware overhead.

Use of the software structure for model synthesis of positional redundant number systems

The article deals with two areas for further research. The first is to increase the speed of arithmetic units by introducing redundancy, and the second - to improve the reliability of computer technology through the introduction of redundancy by reducing their complexity. The aim is to introduce redundancy based on a study of binary-ternary and binary-senary positional number systems. As a result of the effect of the expression of information redundancy in the hardware is made calculation of weight coefficients of positional number systems, and deduced a mathematical model of the error checking device. The rules of the operation of addition are formulated, which made it possible to analyze the binary-ternary and binary-senary positional numeral systems for improving the speed of operation of the adder and increase hardware redundancy. According to the expression it is estimated amount of the proposed model variants of positional number systems – the forms of information required for further computational experiment. Software modules necessary for the models of positional number systems are defined. A number of requirements to the input information redundancy are defined on their basis. Therefore, introduced information redundancy can reduce the complexity of implementing an adder, while ensuring the required performance.

Reliability Measures of a Computer System with Priority for Repair and Hardware Redundancy

This paper concentrates on the evaluation of reliability measures of a computer system by introducing the concept of priority of hardware repair over software up-gradation. The system operates with one more hardware in cold standby. The failure times of hardware and software are independent random variables which follow negative exponential distribution. The repair facility (called server) attends the faults immediately which occur during operation of the system. Repair of the hardware is done at failure while software undergoes for up-gradation. The distributions of hardware repair and software up-gradation times are taken as arbitrary with different probability density functions. The system model has been analyzed using semi-Markov process and regenerative point technique. The trends of some important measures of system effectiveness have been observed for arbitrary values of the parameters. The profit of the present model has also been compared with that of the system model in which no priority is given to hardware repair.

Design of passive fault-tolerant controllers of a quadrotor based on sliding mode theory

Abstract In this paper, sliding mode control is used to develop two passive fault tolerant controllers for an AscTec Pelican UAV quadrotor. In the first approach, a regular sliding mode controller (SMC) augmented with an integrator uses the robustness property of variable structure control to tolerate partial actuator faults. The second approach is a cascaded sliding mode controller with an inner and outer SMC loops. In this configuration, faults are tolerated in the fast inner loop controlling the velocity system. Tuning the controllers to find the optimal values of the sliding mode controller gains is made using the ecological systems algorithm (ESA), a biologically inspired stochastic search algorithm based on the natural equilibrium of animal species. The controllers are tested using SIMULINK in the presence of two different types of actuator faults, partial loss of motor power affecting all the motors at once, and partial loss of motor speed. Results of the quadrotor following a continuous path demonstrated the effectiveness of the controllers, which are able to tolerate a significant number of actuator faults despite the lack of hardware redundancy in the quadrotor system. Tuning the controller using a faulty system improves further its ability to afford more severe faults. Simulation results show that passive schemes reserve their important role in fault tolerant control and are complementary to active techniques

Built-In Self Test and Self-Repairing Circuit for Array Multipliers

Background/Objectives: As the size of the chip reduces, nanoscale devices have become more susceptible to manufacturing faults, interference from radiations and transient faults. Many of these errors are not permanent but it causes malfunctioning of circuit either due to the complexity of the circuit or due to the interaction with the software. In this paper, an area and power efficient BIST with self repairing technique has been proposed, which detect and repair the faults in the circuit. Methods/Statistical Analysis: In this research work, a novel Built-In Self-Test (BIST) architecture with self repairing circuit is proposed. The novelty of this architecture is that testing is done along with the self repairing. The Self repairing circuit repairs the fault in the circuit during testing phase itself which increases the reliability of the circuit. Since the insertion of test pattern externally, BIST architecture does not alter the basic multiplier structure. Findings: Average power dissipation of the proposed Built-in self test and self repairing of array multiplier architecture is reduced by 36% since the use of a power efficient test pattern generator. Self repairing has been accomplished by the use of hardware redundancy technique. Also a TMR based self repairing architecture for real time self repairing has been proposed and its area and power dissipation is compared with the other self repairing architecture. Result shows that the BIST with repairing technique is good for low power applications while the TMR based self repairing method is good for real time self repairing applications. The proposed technique can be extended to self repairing processor.

A Smart Lighting System for Visual Comfort and Energy Savings in Industrial and Domestic Use

The goal of this work is to develop a smart light-emitting diode lighting system for industrial and domestic use with several advantages over conventional systems, namely energy saving, high reliability, and visual comfort of interior lighting. This is achieved by integrating a smart control module and a fault diagnosis and prognosis module within a conventional lighting system. The first module controls the lighting level in an energy-efficient way, keeping a desired light level where it is needed while regulating it to a minimum where not required; this is achieved by fully exploiting fuzzy logic and proportional-integrative-derivative controllers. The second module performs fault diagnosis on the light-emitting diode system and predicts when light-emitting diode maintenance should be performed; this is achieved by employing both hardware redundancy and signal-based approaches. Interaction between the two modules permits maintenance of a desired level of light even in the case of failures on one or more light-emitting diodes. The overall system has been experimentally validated in three different scenarios.

A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors

Advances in CMOS technology have made digital circuits and systems very sensitive to manufacturing variations, aging, and/or soft errors. Fault-tolerant techniques using hardware redundancy have been extensively investigated for improving reliability. Quadded logic (QL) is an interwoven redundant logic technique that corrects errors by switching them from critical to subcritical status; however, QL cannot correct errors in the last one or two layers of a circuit. In contrast to QL, quadded transistor (QT) corrects errors while performing the function of a circuit. In this brief, a technique that combines QL with QT is proposed to take advantage of both techniques. The proposed quadded logic with quadded transistor (QLQT) technique is evaluated and compared with other fault-tolerant techniques, such as triple modular redundancy and triple interwoven redundancy, using stochastic computational models. Simulation results show that QLQT has a better reliability than the other fault-tolerant techniques (except in the very restrictive case of small circuits with low gate error rates and very short paths from primary inputs to primary outputs). These results provide a new insight for implementing efficient fault-tolerant techniques in the design of reliable circuits and systems.

Data-driven process monitoring and fault tolerant control in wind energy conversion system with hydraulic pitch system

Wind energy is one of the widely applied renewable energies in the world. Wind turbine as the main wind energy converter at present has very complex technical system containing a huge number of components, actuators and sensors. However, despite of the hardware redundancy, sensor faults have often affected the wind turbine normal operation and thus caused energy generation loss. In this paper, aiming at the wind turbine hydraulic pitch system, data-driven design of process monitoring (PM) and diagnosis has been realized in the wind turbine benchmark. Fault tolerant control (FTC) strategies focused on sensor faults have also been presented here, where with the implementation of soft sensor the sensor fault can be handled and the performance of the system is improved. The performance of this method is demonstrated with the wind turbine benchmark provided by MathWorks®.

Fault Detection and Isolation in Inertial Measurement Units Based on Bounding Sets

This work addresses the problem of Fault Detection and Isolation (FDI) for navigation systems equipped with sensors providing inertial measurements and vector observations. Assuming upper bounded sensor noise, two strategies are proposed: i) the first one takes advantage of existing hardware redundancy, requiring at least five sensor measurements to isolate faults; ii) the second approach exploits the analytical redundancy between the angular velocity measurements and the vector observations, by resorting to set-valued observers (SVOs). Necessary and sufficient conditions on the magnitude of the faults are provided, in order to guarantee successful detection and isolation, when hardware redundancy is available. Due to the set-based construction of the methods, none of the solutions generates false detections and no decision threshold is required. Using a simulation scenario, the proposed strategies are compared with two alternatives available in the literature.

The MAVEN Magnetic Field Investigation

The MAVEN magnetic field investigation is part of a comprehensive particles and fields subsystem that will measure the magnetic and electric fields and plasma environment of Mars and its interaction with the solar wind. The magnetic field instrumentation consists of two independent tri-axial fluxgate magnetometer sensors, remotely mounted at the outer extremity of the two solar arrays on small extensions (boomlets). The sensors are controlled by independent and functionally identical electronics assemblies that are integrated within the particles and fields subsystem and draw their power from redundant power supplies within that system. Each magnetometer measures the ambient vector magnetic field over a wide dynamic range (to 65,536 nT per axis) with a quantization uncertainty of 0.008 nT in the most sensitive dynamic range and an accuracy of better than 0.05%. Both magnetometers sample the ambient magnetic field at an intrinsic sample rate of 32 vector samples per second. Telemetry is transferred from each magnetometer to the particles and fields package once per second and subsequently passed to the spacecraft after some reformatting. The magnetic field data volume may be reduced by averaging and decimation, when necessary to meet telemetry allocations, and application of data compression, utilizing a lossless 8-bit differencing scheme. The MAVEN magnetic field experiment may be reconfigured in flight to meet unanticipated needs and is fully hardware redundant. A spacecraft magnetic control program was implemented to provide a magnetically clean environment for the magnetic sensors and the MAVEN mission plan provides for occasional spacecraft maneuvers - multiple rotations about the spacecraft x and z axes - to characterize spacecraft fields and/or instrument offsets in flight.

Experimental Evaluation of Data Fusion Algorithm for Residual Generation in Detecting UAV Servo Actuator Fault

Unmanned Aerial Vehicles used by military are generally designed with very high reliability and have multiple redundancy of software and hardware equipment because they are intended to operate in hostile environment. But, relatively low cost UAVs used commercially are not equipped with such systems. Usually, micro UAVs weight less than 2kg are equipped with on-board miniature sensor and operate without any hardware redundancy and thus could reduce their reliability. Some of these commercial UAVs that operate in populated areas will cause damage and fatality if faulty system occurred. Hence there is a need for on-board fault detection and isolation system without degradating the UAV flyability and its cost. Analytical redundancy or model reference method of fault detection algorithms could be implemented as most UAVs are microcontroller controlled. Together, with the availability of miniature sensors could provide an ideal platform for implementing fault detection. In this paper, the development of fault detection through residual generation algorithm is implemented with data fusion from miniature sensors. Some of these sensors are already installed within the autopilot system which reduce the amount of additional sensors needed. Identification of fault in the elevator is simulated experimentally and fault detection rate is monitored. From the implemented algorithm, the data fusion from additional sensors shows improvement in fault detection rate.

Corrective control for transient faults with application to configuration controllers

A novel design methodology of corrective control is proposed for fault-tolerance against transient faults in input/output asynchronous sequential machines. The main objective is to lessen controller complexity by proposing a structure of corrective control that employs no state observer, which is required in the former studies for input/output control of asynchronous machines. The form of the output feedback is also simplified as a unit character instead of bursts. Although the exact identification of the machine's state is infeasible, the proposed controller achieves immediate fault-tolerance against transient faults that cause unauthorised state transitions. As a case study, the authors apply the proposed control scheme to implementing configuration controllers for space-borne field programmable gate array with hardware redundancy in which single event upset faults may happen by the radiation effect.