Hard Switching Conditions Research Articles

Dynamic on‐state resistance instability characterization of a multi‐chip‐GaN MIS‐HEMTs cascode power module

AbstractThe dynamic on‐state resistance instability of a high‐current cascode multi‐GaN‐chip power module under high frequency and voltage switching conditions is demonstrated in this paper. The presented double pulse test topology is utilized to evaluate switching dependencies on voltage, current, and frequency, showing its versatility in investigating the switching instability of the device. The extended defects in the buffer layer resulted in a decrease in dynamic on‐state resistance (RDS‐ON) under hard switching conditions. Despite this, no noticeable RDS‐ON degradation occurs under harsh switching conditions due to electron de‐trapping. This study comprehensively analyzes the dynamic stability of a multi‐GaN‐chip cascode module with devices.

Paralleled multi-GaN MIS–HEMTs integrated cascode switch for power electronic applications

A cascode gallium nitride (GaN) switch integrating four paralleled GaN depletion-mode metal–insulator–semiconductor–high-electron-mobility transistors (MIS–HEMT) and a silicon MOSFET (Si-MOSFET) is presented. Each GaN chip is wire-bonded into a multi-chip power module to scale up the power rating. An optimized symmetric configuration and wire bonding of an integral package are used in the cascode switch. By utilizing an optimized packaging approach, the performance of the multi-GaN-chip cascode switch was evaluated through both static and dynamic characterizations. The constructed cascode switch provides a low-static on-state resistance of 72 mΩ and an off-state blocking capability of 400 V with a positive threshold voltage of 2 V. Analysis of dynamic switching characteristics are discussed and demonstrates stable dynamic on-state resistance (R DS-ON) in inductive load circuits with switching dependencies of voltage, frequency, time, and temperature. The extended defects from buffer caused a minimal decrease in dynamic and static R DS-ON with respect to hard switching conditions. However, there was no noticeable degradation in R DS-ON under harsh switching conditions. This study provides a complete analysis of the multi-GaN-chip cascode switch, including MIS–HEMT manufacturing, cascode packaging and static and dynamic characterizations.

Extraction of Dynamic Threshold Voltage in Resistive Load Hard Switching Operation of Schottky-Type p-GaN Gate HEMT

Threshold voltage (VTh) drift of Schottky-type p-GaN gate high-electron mobility transistor (HEMT) was analyzed under high-voltage and hard switching conditions with a resistive load (R-Load). To overcome the distortion in the drain current (ID) – gate voltage (VG) curve caused by the internal drain capacitance (IDisp) charging current during the switching transients, a method is presented to accurately measure dynamic VTh through appropriate correction of IDisp. The dynamic variation of VTh was tracked with a gate-drive rise/fall times of 200 ns. During the switching operation, VTh increases rapidly at the beginning and then saturates at a stable value. This is attributed to the gate forward current during turn-on that increases the hole depletion of the p-GaN gate through the AlGaN barrier. The dynamic VTh increases linearly at a rate of 40% with the increase of gate turn-on voltage. VTh is independent of duty cycle but minorly increases with frequency at high voltages, suggesting that channel hot electrons be injected into the AlGaN barrier and p-GaN.

A novel zero voltage transition boost converter and artificial neural network‐based estimation of converter efficiency

AbstractIn this paper, a novel zero voltage transition (ZVT) boost converter is proposed, and the overall efficiency of the converter is predicted with an artificial neural network (ANN) model. In the proposed converter, the main switch is turned on by ZVT and turned off by zero voltage switching (ZVS). Also, the other semiconductor elements operate by soft switching (SS). Besides, the proposed snubber cell has the bidirectional direct power transfer feature. The theoretical analyzes of the converter are verified by an prototype having 50 VDC input voltage, 100 VDC output voltage, 250 W output power, and 100 kHz switching frequency. The overall efficiency of the converter in hard switching (HS) condition is increased from 87.2% to 95.4% thanks to proposed snubber cell. Moreover, the efficiency of converter at HS operation is estimated with ANN. For this estimation, 110 efficiency values are obtained based on the different switching frequency and the output power values. When the actual efficiency measurements and the estimation results obtained with the ANN model are compared, it is seen that the results overlap and is obtained very close result to the truth by ANN. Thus, owing to the ANN model, the semiconductor power elements will not need to be operated at high frequencies and overheating, and the damaging to the elements will be prevented. Finally, the efficiency curve measurement of the converter takes long time in the experimental study when it takes highly short time as a few minutes in the estimation with ANN.

Mechanism Analysis of Dynamic On-State Resistance Degradation for a Commercial GaN HEMT Using Double Pulse Test

The dynamic on-resistance (RON) behavior of one commercial GaN HEMT device with p-GaN gate is investigated under hard-switching conditions. The non-monotonic performance of dynamic RON with off-state voltage ranging from 50 to 400 V is ascribed to the “leaky dielectric” model. The highest normalized RON value of 1.22 appears at 150 and 200 V. The gradual increase and following maximum of dynamic RON are found when the device is exposed to a stress voltage for an extended stress time under 100 and 200 V, which is due to a much longer trapping time compared to detrapping time related to deep acceptors and donors. No obvious RON degradation, thanks to the suppressed trapping effect, is observed at higher VDS. From the multi-pulse test, the dynamic RON is seen to be insensitive to the frequency. It is demonstrated that the leakage, especially under source and drain contact, is a key issue in the dynamic resistance degradation.

Modeling and Analysis of N-Branch Hybrid Switched Inductor and Capacitor Converter

This paper proposes a family of N-Branch hybrid switched inductor and capacitor (SLC) converters. With the single circuit, the multi-level output voltage or current could be generated. The proposed converter is suitable both for the voltage source and the current source. The same LC network is reused for different LC branches. The proposed converter is controlled by the phase shift control method with a time domain multiplexing concept. The N level circuit is operated with the same frequency. One cycle period is divided into N small time cycles for each branch. The phase shift for each branch is 360°/N. The load voltage could be changed by modifying the duty cycle of the transistor. When the SLCs work in the resonant condition, the soft switching will be acquired. The power loss of transistors could be sharply reduced. In this paper, a 300 W SLC converter is constructed to verify the theoretical analysis and operation mechanism in the resonant condition and hard switching condition. With the experimental and simulated verification, the soft switching and the stable multi-level output voltage or current are achieved. The proposed SLC converter could be used for the multi-level voltage power supply system, such as the electric vehicle, the electric aircraft, autonomous underwater vehicles (AUVs) and a new energy generation system.

Degradation of SiC MOSFETs Under High-Bias Switching Events

Evaluating the robustness of power semiconductor devices is key for their adoption into power electronics applications. Recent static acceleration tests have revealed that SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the high-bias robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc bias higher than the device rated voltage. Under this high-bias switching condition, SiC MOSFETs show degradation in merely tens of hours at 25 °C and tens of minutes at 100 °C. Two independent degradation and failure mechanisms are unveiled: one present in the gate oxide and the other in the bulk-semiconductor regions, featured by the increase in the gate leakage current and the drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along with the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. These results suggest the insufficient robustness of SiC MOSFETs under high-bias, hard-switching conditions and the significance of using switching-based tests to evaluate the device robustness.

Understanding the effects of off-state and hard-switching stress in gallium nitride-based power transistors

The aim of this paper is to improve the understanding of gallium nitride (GaN) high electron mobility transistors (HEMTs) submitted to hard switching operation, with focus on the hot-electron phenomena. This is becoming a hot-topic both for the scientific community and for the industry. The analysis is carried out through a cross-comparison of three different experimental techniques: conventional Pulsed-IV characterization, a novel pulsed-drain current transient (P-DCT) method, and a custom-developed hard switching test protocol. Hard switching analysis was performed through a novel system able to test the device in hard-switching conditions with an unprecedented turn-on slew-rate of 25 V ns−1 on-wafer level. This allows μs to investigate the impact of hard switching in terms of (i) locus trajectory, (ii) dissipated power, and (iii) dynamic increase. Furthermore, the accumulation of switching stress is assessed by repeating the experiment with increasing frequency, from 1 kHz to 100 kHz. The extensive cross-analysis offers a novel insight on the degradation mechanisms occurring in power GaN HEMTs. The results collected within this paper allow: (1) to evaluate the dynamic behavior under both soft- and hard-switching stress, thus differentiating off-state and semi-on-state stress; (2) to pinpoint hot-electrons as the main cause of the current collapse observed in semi-on; (3) by comparing the results obtained from P-DCT and Hard Switching Analysis we demonstrate that the hot-electron trapping is a very fast process which can happen in few ns. The related trapping and de-trapping kinetics are investigated in detail. The results described within this paper provide novel insight on the important role of hot-electrons in the dynamic increase during hard switching operations.

A novel on-wafer approach to test the stability of GaN-based devices in hard switching conditions: Study of hot-electron effects

In this work, a novel system to investigate the stability of GaN-based HEMT devices is presented and used to investigate hot-electron effects. The developed system is used to study the impact of hard switching on the dynamic on-resistance of such devices. In particular, we were able to obtain (on-wafer level) a very fast turn-ON commutation with dVDS/dt ≈ 10 V/ns (representative of realistic conditions) thanks to the low parasitics at the drain node. As a result, a realistic performance assessment of the dynamic stress of GaN power HEMTs is now available on wafer level, thus shortening the technology development loop. By intentionally tuning the capacitance at the drain node we can accurately control the amount of energy/charge released during each hard switching event, thus being able to evaluate the impact of increasing stress conditions on the devices. The results indicate that even if the hard-switching lasts few nanoseconds, it significantly impacts the dynamic RDSON: we conclude that hot-electron trapping can occur in ns-time scale.

An Improved Methodology for Switching Losses Estimation in SiC MOSFETs


 This work presents an improved analytical model concerning the prediction of switching losses in power MOSFETs by considering the influence of parasitic elements in the high-frequency operation of devices. By using the transistor voltage and current waveforms, it is possible to predict switching losses under hard-switching conditions adopting only parameters that can be obtained from the device datasheet. The method employs the nonlinearities associated with the junction capacitances, which are incorporated into the model through curve fitting. Besides, the sensitivity analysis is used to identify which parameters have a major influence on the estimated losses. The methodology is described in details and verified by means of experimental results concerning a SiC MOSFET, which is tested under various current and voltage conditions

A Self-Regulating Gate Driver for High-Power IGBTs

To gain accurate control of the whole switching transients, this article proposes a self-regulating voltage-source gate drive (SRVSD) method for high-power insulated gate bipolar transistors (IGBTs) working under hard switching conditions. The SRVSD has a high-speed circuit capable of adjusting drive levels. With high-speed feedbacks, the on-board field programmable gate array (FPGA) identifies each switching stage and accordingly varies drive voltages. In this way, switching delay, diC/dt and dvCE/dt are regulated individually. The SRVSD allows accelerated delays and dvCE/dt stages without increasing diC/dt. Based on their principles, SRVSD is compared with existing active drivers comprehensively to verify its delay and loss reductions performance. By experiments, compared to conventional gate drive (CGD), SRVSD achieves at most 80%, 72% reductions in turn-on and turn-off delays, and 58%, 31% reductions in turn-on and turn-off losses at identical current/voltage overshoots. Moreover, the proposed adaptive control concept is verified in this article. Within several cycles, this concept automatically regulates durations of all delay, diC/dt and dvCE/dt stages to reach individual target values, largely independent of switching conditions. A practical piecewise linear switching-based loss model is proposed. Combined with SRVSD, this practical loss model can offer convenient sensing and control of switching losses in an accurate and online manner.

Fast System to measure the dynamic on‐resistance of on‐wafer 600 V normally off GaN HEMTs in hard‐switching application conditions

This study presents a novel system to investigate the on-wafer level dynamic properties of GaN-based power transistors in hard-switching application conditions. The system is able to analyse devices with an on-resistance (RDSON) in the range from few ohms to hundreds of ohms, and can be effectively used to improve the development process of GaN high electron mobility transistors (HEMTs) power devices at the wafer level. Contrary to the conventional double-pulse setup, where a resistive load is usually used in combination with a very low duty cycle, the dynamic RDSON is acquired during realistic operating conditions, in a boost converter circuit. Consequently, the authors’ system is able to study not only the field-activated trapping processes, but also those induced by hard-switching conditions, i.e. promoted by hot electrons and self-heating. The maximum working voltage (600 V) and the minimum RDSON measurement time after turn-on (2 µs) allow evaluating the operation limit of the devices in a voltage/frequency range close to real switching conditions. Working on the wafer level allows a more realistic assessment of the dynamic RDSON behaviour before the packaging phase, which is very important to improve the production and development process of GaN-HEMT devices.

Common‐ground non‐isolated high‐gain DC/DC converter for low powerdistributed generation photovoltaic systems

A high step-up/high-efficiency converter is one of the essential requirements of a low power grid-connected photovoltaic system that provides the maximum power point tracking ability and injects the low voltage extracted power to AC or DC distribution network. This study presents a common-ground non-isolated high-gain DC/DC converter whit a naturally wide range of soft-switching conditions. The proposed converter has two resonant loops, and a new simple structure consists of an active switch, three diodes, two inductors and two capacitors, work in two useful operation modes. In the optimum operation mode (OOM), the switch turns on/off in zero current switching (ZCS)/zero voltage switching condition, and at the sub-OOM, the switch turns on in ZCS condition and turns off in hard switching condition. The mathematical analysis and MATLAB/SIMULINK simulation results are described in detail. Also, a prototype 100 W converter is built and tested to validate the simulation analysis on a 100 W photovoltaic panel.

Characterization of 3.3-kV Reverse-Blocking SiC Modules for Use in Current-Source Zero-Voltage-Switching Converters

Silicon carbide (SiC) MOSFETs with ratings of 3.3 to 15 kV represent a dramatic improvement over available silicon devices, enabling the realization of medium-voltage converters in demanding applications such as solid-state transformers. Typical voltage-source converter configurations realize significant reduction in switching loss with SiC devices, but high dv/dt of 30–50 kV/ μ s generates high levels of electromagnetic interference (EMI) and displacement currents. Current-source based zero-voltage switching (CS-ZVS) converters such as the soft-switching solid-state transformer (S4T), dramatically reduce switching loss using ZVS, thus realizing both controlled dv/dt and low EMI. CS-ZVS converters require reverse blocking (RB) modules that are realized using series connection of a diode and a MOSFET. However, no data are available from manufacturers or from literature on RB module characterization under ZVS conditions. This article presents detailed characterization results and model extraction for a 3.3 kV 45 A and a 1.7 kV 10 A SiC RB module, under both hard switching and ZVS modes. A novel double-pulse testbed is designed and built for this characterization of RB devices under both hard switching and ZVS conditions. Significantly, it is shown that when the RB modules are used in CS-ZVS converters, the dynamic voltage sharing between the RB modules in a phase leg and within the RB module (between the diode and the switch) results in a unique voltage stress. Modulation strategies to address this unique voltage stress are proposed and verified through experiment results, using a S4T prototype rated at 1.5 kV, 10 kVA .

CSTBT™ technology for high voltage applications with high dynamic robustness and low overall loss

This paper discusses the edge termination design of high-voltage insulated gate bipolar transistors with large current turn-off switching operation. We discovered that the phenomena of current crowding and impact ionization act as separated heat sources and induce one local hot spot that causes thermal destruction in the edge termination during the turn-off switching period. Optimizing the backside hole injection efficiency and relaxing the electric field of the surface pn junction edge at the edge termination region prevent the above problems. These concepts benefit the dynamic ruggedness under hard-switching conditions. This paper presents our novel edge termination design that achieves robust turn-off capability without deteriorating other performances of the device.

Test Setup for Dynamic ON-State Resistance Measurement of High- and Low-Voltage GaN-HEMTs Under Hard and Soft Switching Operations

GaN-HEMTs impress with excellent properties, and therefore power electronics engineers pay a lot of attention to them. However, during switching operation some devices show increased ON-state resistance. Since, for switch mode power supply designers, the internal device structure is not apparent, measuring the ON-state resistance under the targeted operating conditions is the only method to gain this information. In order to characterize the dynamic ON-state resistance, this article proposes a clamping circuit for accurate measurement. Using a high-resolution digitizer card ensures precise results. The presented measurement setup allows to measure the ON-state resistance under hard and soft switching conditions with parameters of the intended application. In inverter applications, each switch works under hard as well as soft switching. Therefore, the transition between these two operating modes must also be studied in detail. Finally, an extension of the clamping circuit is presented allowing measurements with high-voltage GaN-HEMTs as well. The initial results verify the improved setup.

New active snubber cell for high power isolated PWM DC–DC converters

Here, a new active snubber cell for high-power isolated pulse-width-modulated (PWM) DC–DC converters is proposed. All semiconductor power devices in the proposed converters operate with full soft switching under a very wide load range, and they are not exposed to any voltage and current stress. The main switches turn on with zero-voltage transition (ZVT) and turn off with zero-voltage switching (ZVS). The auxiliary switches turn on with zero-current switching (ZCS) and turn off with ZVS. The theoretical analysis and design procedure for the proposed active snubber cell are carried out in detail and are verified with a half-bridge (HB) converter implementation having 20V output voltage, 50 A output current, and 80 kHz switching frequency. The overall efficiency of the HB DC–DC converter is increased from about 83% in the hard switching condition to about 90% thanks to the proposed active snubber cell.

Open-Loop Gate Control for Optimizing the Turn-ON Transition of SiC MOSFETs

This paper presents a novel open-loop gate control of the turn-ON transient for SiC MOSFETs in hard switching conditions. The gate control could reduce the SiC MOSFETs turn-ON gate voltage overshoot and control turn-ON $di/dt$ and $dv/dt$ independently. Because of the high turn-ON speed, SiC MOSFETs bring serious electromagnetic interference (EMI) in the half-bridge topology. A conventional gate driver decreases EMI by increasing the gate resistor, but clearly increasing the turn-ON loss. To address this tradeoff and optimize SiC MOSFETs turn-ON transition, the drain current slope and the drain–source voltage slope are controlled independently by controlling the gate–source voltage profile during the current rise phase and the gate current during the voltage falling phase. In addition, gate voltage overshoot is considered and discussed. By adding a considerably higher gate resistance during the ON-state operation stage, gate voltage overshoot is almost nonexistent while maintaining low turn-ON loss. The experimental verifications of the proposed approach are finally conducted, and the advantages of proposed driver are analyzed and discussed.

Gate Control Optimization of Si/SiC Hybrid Switch for Junction Temperature Balance and Power Loss Reduction

The hybrid switch concept of paralleling a higher-current main Si IGBT and a lower-current auxiliary SiC mosfet offers an improved cost/performance tradeoff in power converters. Currently, the gate control strategy of these two internal devices emphasizes on minimizing the total power loss, and is referred to as the efficiency control mode in this paper. However, there is a serious risk of overheating and reliability degradation of the SiC mosfet if solely relying on this control strategy. In this paper, we propose a new method of gate control optimization, referred to as the thermal balance control mode, to keep the junction temperature of both devices within the specified temperature range, and to minimize the total power loss simultaneously. We first investigate the dependency of the hybrid switch switching losses on the gate control pattern both theoretically and experimentally. We then extensively study control optimization in these two distinct control modes in a dc–dc boost converter. It is found that the thermal balance control mode can achieve almost the same total power loss as the efficiency control mode, but much lower and more balanced junction temperatures of the two internal devices. Experimental results demonstrate that the Si/SiC hybrid switch in an optimal thermal balance control mode can achieve a 163% higher power handling capability in the 20-kHz boost converter or four times higher switching frequency in the 4-kW boost converter than a single IGBT solution with hard switching condition, and yet a considerably lower component cost than a single SiC mosfet solution in the boost converter.

A Simple Closed-Loop Active Gate Voltage Driver for Controlling diC/dt and dvCE/dt in IGBTs

The increase of the switching speed in power semiconductors leads to converters with better efficiency and high power density. On the other hand, fast switching generates some consequences like overshoots and higher switching transient, which provoke electromagnetic interference (EMI). This paper proposes a new closed-loop gate driver to improve switching trajectory in insulated gate bipolar transistors (IGBTs) at the hard switching condition. The proposed closed-loop gate driver is based on an active gate voltage control method, which deals with emitter voltage (VEe) for controlling diC/dt and gets feedback from the output voltage (vCE) in order to control dvCE/dt. The sampled voltage signals modify the profile of the applied gate voltage (vgg). As a result, the desired gate driver (GD) improves the switching transients with minimum switching loss. The operation principle and implementation of the controller in the GD are thoroughly described. It can be observed that the new GD controls both dvCE/dt and diC/dt accurately independent of the variable parameters. The new control method is verified by experimental results. As a current issue, the known trade-off between switching losses and EMI is improved by this simple and effective control method.