Open-Loop Gate Control for Optimizing the Turn-ON Transition of SiC MOSFETs

Abstract

This paper presents a novel open-loop gate control of the turn-ON transient for SiC MOSFETs in hard switching conditions. The gate control could reduce the SiC MOSFETs turn-ON gate voltage overshoot and control turn-ON $di/dt$ and $dv/dt$ independently. Because of the high turn-ON speed, SiC MOSFETs bring serious electromagnetic interference (EMI) in the half-bridge topology. A conventional gate driver decreases EMI by increasing the gate resistor, but clearly increasing the turn-ON loss. To address this tradeoff and optimize SiC MOSFETs turn-ON transition, the drain current slope and the drain–source voltage slope are controlled independently by controlling the gate–source voltage profile during the current rise phase and the gate current during the voltage falling phase. In addition, gate voltage overshoot is considered and discussed. By adding a considerably higher gate resistance during the ON-state operation stage, gate voltage overshoot is almost nonexistent while maintaining low turn-ON loss. The experimental verifications of the proposed approach are finally conducted, and the advantages of proposed driver are analyzed and discussed.