Degradation of SiC MOSFETs Under High-Bias Switching Events

Abstract

Evaluating the robustness of power semiconductor devices is key for their adoption into power electronics applications. Recent static acceleration tests have revealed that SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the high-bias robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc bias higher than the device rated voltage. Under this high-bias switching condition, SiC MOSFETs show degradation in merely tens of hours at 25 °C and tens of minutes at 100 °C. Two independent degradation and failure mechanisms are unveiled: one present in the gate oxide and the other in the bulk-semiconductor regions, featured by the increase in the gate leakage current and the drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along with the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. These results suggest the insufficient robustness of SiC MOSFETs under high-bias, hard-switching conditions and the significance of using switching-based tests to evaluate the device robustness.