Half Adder Research Articles

Coupled Electrical–Thermal–Fluidic Multi-Physics Analysis of Through Silicon Via Pin Fin Microchannel in the Three-Dimensional Integrated Circuit

Abstract To solve the thermal management problem in the three-dimensional integrated circuit (3D-IC) with high integration and multilayer, this paper establishes a 3D-IC interlayer microchannel model with various embedded TSV micropin fins to explore the temperature distribution of chips and the flow velocity distribution inside the microchannel. The paper selects the sense amplifier and the half adder as the heat source of the memory and processor in the calculation model. The power densities of the sense amplifier and the half adder are 885 kW/m2 and 1.832 MW/m2 combined with the layout size, respectively. Meanwhile, the effects of the shape and arrangement of TSV micropin fins on the flow and heat transfer characteristics are investigated. The result shows that the 1.2:1 diamond micropin fin microchannel with staggered arrangement has the best overall flow and heat transfer performance. Compared with the basic circular micropin fin with the in-line arrangement, the average Nusselt number of this microchannel is improved by 3.20–3.37 times, and the maximum temperature of chips is controlled at 325.92–312.43 K for Re = 628–1819.

Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing

In this paper, we propose a non-traditional design of dynamic logic circuits using Fully-Depleted Silicon on Insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_t</i> ) to be adjustable (i.e., low-Vt and high-Vt states) by using the back gate bias. Our design utilizes the front and back gates of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like; NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like; half adder and full adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates.

Design of All-Optical Logic Half-Adder Based on Photonic Crystal Multi-Ring Resonator

In this paper, a novel design of an all-optical half-adder (HA) based on two two-ring resonators in a two-dimensional square-lattice photonic crystal (PC) structure without nonlinear materials is proposed. The all-optical HA comprises AND and XOR gates where each gate is composed of cross-shaped waveguides and two-ring resonators in a 2D square-lattice PC that are filled with silicon (Si) rods in silica (SiO2). The AND and XOR gates are analyzed and simulated using plane-wave expansion (PWE) and finite-difference time-domain (FDTD) methods. Simulation results show that light guiding inside the device functions as AND and XOR gates. Thus, the proposed device has the potential for use in optical arithmetic logic units for digital computing circuits. The structure comprises an optical AND gate and an optical XOR gate that were designed to work at the C-band spectrum. Results show that there is a clear distinction between logic states 1 and 0 with a narrow power range that leads to a better robust decision on the receiver side for minimized logic errors in the photonic decision circuit. Thus, the proposed HA can be a key component for designing a photonic arithmetic logic unit.

Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units

This paper proposes a new Two-Stage Carry Select Adder (TSCSA) using a single type of leaf cell i.e., a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed with three stages. The first stage produces the result with input carry ‘0’, the second stage generates an excess-1 result and the third stage is used to select one of the results using multiplexers. The proposed 4-, 8-, 16-, 32-, and 64-bit TSCSA are distinctly designed in two stages only. The carry propagation through adders and full adders is completely eliminated which is the main bottleneck problem for high-speed arithmetic units. A 64-bit TSCSA is distinctly decomposed for maintaining excellent cell regularity that uses one type of cell i.e., 2-1multiplexer. Ripple carry adder blocks in existing designs are replaced with half adders by eliminating the carry propagation. At the outset, the speed of TSCSA is improved by overcoming carry propagation through adder blocks, especially in higher-order adders. The area is the major concern for CaSeAs; is also reduced for TSCSA by maintaining cell regularity. Verilog HDL is used in the design of the TSCSA and existing CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At the 90 nm technology node, all of the designs are generated and executed using Cadence Genus and Innovus, respectively. In comparison to current designs, there is marginal improvement in area and power but there is substantial improvement in speed. The proposed 64-bit TSCSA final ASIC architecture is 9% more compact and dissipates 13% less power. According to the comparison and result analysis, TSCSAs have 69% superior speed than existing designs. As a result, TSCSA works best in low-power, small-area, and fast applications.

Implementation of Full Adder Using Nand Gates

: In digital electronics, there are different types of logic circuits used to perform different kinds ofarithmetic operations. One of them is adder. Adder (or Binary Adder) is a combinational logic circuit that performs the addition of two or more binary numbers and gives an output sum. There are two types of adders present namely, half adder and fulladder. Since, adder are logic circuits, thus they are implemented using different types of digital logic gates such as OR gate, AND gate, NOT gate, NAND gates, NOR gates, etc. In this article, we will discuss the Full Adder Realization using NAND Gates. But before that let’s have a look into the basics of full adder.

VLSI Design of Approximate Baugh-Wooley Multiplier for Image Edge Computing

A sort of digital circuit used to multiply two binary values is called a Baugh-Wooley multiplier. It is renowned for being more effective than other kinds of multipliers in terms of speed and gate count. You would normally start by creating a simple version of the circuit utilizing logic gates like AND gates, XOR gates, and half adders to simulate the Baugh-Wooley multiplier. The design would then be optimized utilizing methods like parallel processing, pipelining, and optimization algorithms to lower the overall gate count and boost the functionality of the circuit. Because of this, estimating a Baugh-Wooley multiplier would require a thorough knowledge of these elements as well as the specifications of the application. Verilog HDL is used to implement this design, and Modelsim 6.4 c is used to simulate it. The synthesis process tool from Xilinx measures performance.

Design of Fault Tolerant Array Multiplier Using Parity Preserving Reversible Gate

The digital designs with Reversible logic are more popular now days because of the increased demand of low power usage. Some of the Reversible logic gates are discussed in this paper. This paper also introduces a Parity Preserving Reversible Gate (PPRG) which is used in the fault tolerant devices design such as adders, subtractors and multipliers. The design of an array multiplier by using fault tolerant parallel adders is discussed in this paper. The fault tolerant parallel adders are designed using fault tolerant full adders and half adders and these adders are designed through Parity Preserving Reversible Gate. These adders and multipliers are useful in designing complex circuits such as ALU.

Carrier Modulation in 2D Transistors by Inserting Interfacial Dielectric Layer for Area-Efficient Computation.

2D materials with atomic thickness display strong gate controllability and emerge as promising materials to build area-efficient electronic circuits. However, achieving the effective and nondestructive modulation of carrier density/type in 2D materials is still challenging because the introduction of dopants will greatly degrade the carrier transport via Coulomb scattering. Here, a strategy to control the polarity of tungsten diselenide (WSe2 ) field-effect transistors (FETs) via introducing hexagonal boron nitride (h-BN) as the interfacial dielectric layer is devised. By modulating the h-BN thickness, the carrier type of WSe2 FETs has been switched from hole to electron. The ultrathin body of WSe2 , combined with the effective polarity control, together contribute to the versatile single-transistor logic gates, including NOR, AND, and XNOR gates, and the operation of only two transistors as a half adder in logic circuits. Compared with the use of 12 transistors based on static Si CMOS technology, the transistor number of the half adder is reduced by 83.3%. Theunique carrier modulation approach has general applicability toward 2D logic gates and circuits for the improvement of area efficiency in logic computation.

Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier

&lt;span lang="EN-US"&gt;In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.&lt;/span&gt;

Energy efficient design of unbalanced ternary logic gates and arithmetic circuits using CNTFET

The emergence of multi-valued logic (MVL) is a substitute to binary logic approaches for realizing high-information density logic systems and high-operating speed systems. In this paper, a design for standard ternary inverter (STI), ternary NAND (TNAND), ternary NOR (TNOR) using carbon nanotube field effect transistors (CNTFETs) is proposed in which a p-type dynamic diode is used with the goal of lowering the energy consumption expressed as power delay product (PDP) and thereby reducing battery usage. Additionally, the basic arithmetic operations are then performed using proposed ternary logic circuits, which can be extended to realize more complex operations. The proposed designs are simulated in HSPICE using a 32 nm Stanford CNTFET model. With respect to variation in process parameters, the reliability of the proposed STI circuit is examined. Simulation results verify that the proposed designs show improvement in terms of power consumption and power delay product (PDP) compared to the other CNTFET based ternary logic circuits. Moreover, less variations are observed in power and PDP of the proposed logic gates with variation in process parameters, capacitance, temperature, frequency and supply voltage. The proposed circuit designs of STI, TNAND, TNOR, ternary half adder (THA), ternary multiplier (TMUL) show 78 %, 98 %, 99 %, 99 %, 99 % improvement in PDP respectively, as compared to the conventional CNTFET based circuit designs and 99 % PDP improvement in all proposed circuits compared to CNTFET based logic circuits with resistive load.

Ultra-compact and low delay time all optical half adder based on photonic crystals

In this paper, an optical half adder is designed using photonic crystals. One of the features of this half adder is its small size. In the design of this structure, it has been tried to have a small size, shorter delay and high contrast ratio so that it can be used in the design of optical integrated circuits. For the sum and carry outputs, the obtained contrast ratio in the designed half adder is 15.4 dB and 7.4 dB, respectively. In addition, the proposed structure has a size of 70 µm2. The small size of this structure and the use of simple point defects, have caused the maximum delay time of this structure to be reduced to 0.07 ps. Due to these characteristics, this structure is suitable for high-speed optical integrated circuits.

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder (M2CSA) using single leaf cell i.e., 2–1 Multiplexer. M2CSA is designed using a new type of Excess-1 block. The Excess-1 block is designed in a distinct way using 2–1 multiplexers. The architectures of the proposed carry select adder and its internal excess-1 blocks are completely distinct when compared to existing carry select adders. The proposed 4-, 8-, 16-, 32-, and 64-bit M2CSAs use a 2–1 multiplexer only. The complex gates such as XOR gates are eliminated which exist in existing Carry Select Adders (CaSeAs). A 64-bit M2CSA that utilises one kind of 2-1 Mux cell is clearly decomposed to retain outstanding cell regularity. In previous designs, ripple carry adder blocks are substituted with half adders by limiting carry propagation to a particular degree. By avoiding carry propagation over adder blocks, particularly in 32- and 64-bit adders, the performance of M2CSA is initially increased. For CaSeAs, the area is of primary significance; for M2CSAs, it is also diminished by preserving cell regularity. Verilog HDL is utilised in the design of the M2CSA and current CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At a 90nm technology node, all of the designs are generated and executed using Genus and Innovus tools, respectively. As a comparison to prior designs, the 64-bit M2CSA final ASIC architecture is on average 17% less in terms of space. The comparison and result analysis show that 64-bit M2CSA performs 20% and 19% faster than 64-bit SQCSC in terms of performance and power dissipation, respectively.. The proposed 4-, 8-, 16-, 32-, 64- bit M2CSA exhibits less PDP (Power-Delay Product) ranging from 25%–30% concerning SQCSCs. Similarly, EDP (Energy- Delay Product) values for all the designs are calculated. The improvement in EDP for the 4-, 8-, 16-, 32-, 64- bit M2CSA is 41, 38, 42, 43, and 45 percentages compared to 4-, 8-, 16-, 32-, 64- bit SQCSC respectively. Therefore, the M2CSAs outperform the existing designs in terms of EDP by 38%–45%.

All-optical half adder and subtractor circuits using cross-phase modulation based switching effect in the phase-shifted fiber Bragg gratings

All-optical half adder and subtractor circuits using cross-phase modulation based switching effect in the phase-shifted fiber Bragg gratings

Design and Analysis of High Speed Multiply and Accumulation Unit for Digital Signal Processing Applications

Unit for Digital Signal Processing Applications&#x0D; &#x0D; Kausar Jahan1, Pala Kalyani2, V Satya Sai3, GRK Prasad4, Syed Inthiyaz5, Sk Hasane Ahammad6&#x0D; 1Department of ECE, Dadi Institute of Engineering and Technology&#x0D; Anakapalle, Andhra Pradesh, India&#x0D; 2Department of ECE, Vardhaman College of Engineering&#x0D; Kacharam, Shamshabad, India&#x0D; 3Department of ECE, Koneru Lakshmaiah Education Foundation&#x0D; Guntur, India-522502&#x0D; 4Department of ECE, Koneru Lakshmaiah Education Foundation&#x0D; Guntur, India-522502&#x0D; 5Department of ECE, Koneru Lakshmaiah Education Foundation&#x0D; Guntur, India-522502&#x0D; 6Department of ECE, Koneru Lakshmaiah Education Foundation&#x0D; Guntur, India-522502&#x0D; &#x0D; Abstract—The fundamental component used in many of the Digital signal Processing (DSP) applications are Multiply and Accumulation Unit (MAC). In the literature, a multiplier consists of greater number of full adders and half adder in partial product reduction stage, which increases the hardware complexity and critical path delay to MAC unit. To overcome this problem, two novel multipliers are proposed in this article. The proposed multipliers are designed and implemented in hardware, which reduces the circuit complexity and improves the overall performance of the MAC unit with less delay. The proposed multipliers are compared with the 4-bit existing designs and observed that the number of slices Look Up Tables (LUTs) are minimized from 113 to 43, Slices are reduced from 46 to 14, Full Adders (FAs) are lessened from 28 to 23, bonded Input Output Blocks (IOBs) and Half Adders (HAs) were not altered. The time delay is reduced from 14.251ns to 7.876ns. The proposed multipliers are compared in the literature with the 8-bit multiplier, then the number of Slice LUTs are reduced from 510 to 231, Slices are reduced from 218 to 113, FAs are reduced from 120 to 110, HAs are reduced from 56 to 39, time delay is reduced from 26.228ns to12.748ns, but bonded IOBs count remains same. The synthesis and simulations results are verified by using Xilinx ISE 14.7 version tool.

Design and Optimization of A 4-bit Absolute-value Detector Using Half Adder and Comparator

In this paper, a design and optimization of a 4-bit absolute value detector is realized by using the CMOS technique, transmission gates, and the traditional comparator, which can compare the two positive input values all expressed in binary form. To optimize the overall performance of the absolute value detector, this paper chooses to minimize the number of transistors and simplifies the circuit through logical analysis. As for calculating the overall delay and energy consumption, critical path identification is also studied and analyzed in this paper. Based on the theory of path effort and path parasitic delay, the grid capacitance and resistance are introduced into the calculation of inverter ratios. To achieve various optimization objectives, this study also combines the grid size and power supply voltage scaling techniques to reduce the delay and energy of the circuit, and finally finds the minimum energy loss at a 1.5x delay. The overall delay and energy can be expressed by the multiple of the unit size inverter of that. As a compromise, a minimum delay of 1.5 times is selected to reduce energy consumption by 39.16 %.

Design and Optimization of 4-bit Absolute-value Detector Based on CMOS

With the development of neural signal acquisition systems, spike-sorting algorithms have been paid full attention. As one of the most extensively used spike-detection algorithms, a 4-bit absolute-value detector is designed in the paper, which comprises three types of architecture. The first design is using combinational logic circuit through a truth table of the absolute value of 2′s complement format and a comparator; the second design is a combination of a series of half adders and transmission gates and a comparator; the third design consists of a combinational logic circuit by truth table of 2′s complement and a cascade of full adders. Then the paper compares the total number of stages and consuming transistors of each circuit, and finally chooses the second circuit, which has five stages and 74 transistors of consumption, as the object of following optimization of critical path delay and energy consumption. With gate sizing, the optimized critical path delay is about 43.05 tp0. The original energy consumption under minimum delay is 49.88C, and the optimized energy consumption under 1.5x minimum delay is 30.35C which is reduced by 39.16%. The processing of the functional realization and circuit optimization of absolute-value detectors can both benefit from the design presented in this work.

Design of multifunctional all-optical logic gates based on photonic crystal waveguides.

The explosive development of the big data era has driven the rapid growth of silicon photonics, and logic operators based on photonic circuits have also been intensively investigated. Photonic integrated logic operators possess a high degree of design freedom and novel prospects, and they are regarded as promising platforms for future signaling and data processing. In this work, considering all-optical logic operation with lower power consumption and a smaller device footprint, multifunctional all-optical logic gates based on silicon photonic crystal (PhC) waveguides and phase-encoded light beams are proposed and applied to realize several logic operators, including XNOR, XOR, NOR, AND gates as well as a half adder and half subtractor. The initial phases (π and 0) of incident light represent the input digital states (1 and 0), and the logic operation results are determined by the output light intensity. Also, simulations are carried out to verify the proposed concept and to investigate the rise time, fall time, and cross talk of the devices. Theoretically, the bit rate for the proposed device can reach 1.25Tb/s, and the proposed structures have the potential to be extremely compact due to PhC waveguides.

Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders

This work presents comparison of ternary combinational digital circuits that reduce energy consumption in low-power VLSI (Very Large Scale Integration) design. CNTFET and GNRFET-based ternary half adder (THA) and multiplier (TMUL) circuits has been designed using ternary unary operator circuits at 32nm technology node and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. The effect of CNTFET and GNRFET parametric variation with threshold voltage on performance metrics namely delay and power has been analyzed. Dependence of threshold voltage on the geometry of carbon nanotube and graphene nanoribbon makes it feasible to be used for ternary logic design. It is analyzed that CNTFET based circuits are energy efficient than the GNRFET- based circuits. It is also concluded that the CNTFET-based circuitshas less power-delay product (PDP) when compared to GNRFET- based circuits. CNTFET-based THA is 23.5% more efficient than GNRFET-based THA and CNTFET-based Tmul is97.8% more efficient than GNRFET-based Tmul.All the digital circuits have been simulated using HSPICE tool.

IMPLY-Based High-Speed Conditional Carry and Carry Select Adders for In-Memory Computing

Big data applications involved with neural networks requires frequent data transfer between memory and processing elements and thus, take a significant portion of energy. One possible method is to realize logic operations inside the memory, often known as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-memory computing</i> . The memristor employed in a crossbar can also conduct logic operations, making it a promising candidate for enabling such designs. In-memory computing can vastly improve speed efficiency by significantly reducing memory access time and energy. Therefore, efficient operations inside the memory are crucial for data-intensive applications. This paper presents two high-speed adders in memristive technology, which are derived using IMPLY-based logic operations and can be implemented on a crossbar architecture for in-memory computing. One is a carry select adder, which uses efficient ripple carry adders and multiplexers. While the other is a conditional carry adder, designed using a modified half adder and multiplexers. An IMPLY-based multiplexer and modified half adder are proposed as part of these adders. A modified half adder calculates the sum of two inputs and two carry outputs for various carry inputs. Compared to conventional adder designs, the speed of these two adders has been significantly enhanced. In particular, the proposed 32-bit Carry Select Adder and Conditional Carry Adder take 123 and 90 computational steps, respectively. The proposed adders have improved the speed by 30 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> and 49 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> , respectively, compared to the best-existing adder in IMPLY. Further, this paper presents computational steps and the number of memristors required for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$n$</tex-math></inline-formula> -bit adders. The proposed circuits were simulated using the VTEAM model, and energy consumed per each adder is calculated from the simulations.

Low power based ternary half adder using fin type field effect transistor technology

Low power based ternary half adder using fin type field effect transistor technology