Graphene Nanoribbon Field-effect Transistors Research Articles

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

Tri-state GNRFET-based fast and energy-efficient ternary multiplier

As silicon field-effect transistors encounter increasing scaling challenges, digital system designers are shifting their attention towards multi-valued logic (MVL), specifically ternary logic. The graphene nanoribbon field-effect transistor (GNRFET) emerges as a compelling alternative among post-MOSFET technologies for the implementation of ternary logic. This paper delves into the computational intricacies of ternary logic, underscores the outstanding features of GNRFET technology, and introduces a novel GNRFET-based 1-trit ternary multiplier (TMUL) requiring only 26 transistors. The performance of the design is assessed using the Synopsis HSPICE simulator with a 32-nm GNRFET model file operating at VDD = 0.9 V. The proposed TMUL surpasses existing designs due to its efficient paths with a minimal number of transistors for each output transition, a singular power supply voltage, and an extended voltage division scheme. In comparison to other contemporary TMUL designs, the proposed design exhibits a notable enhancement, showcasing a 21.42 % reduction in delay, a 33.11 % decrease in power-delay-product (PDP), and a 58.17 % decrease in energy-delay-product (EDP). Additionally, the design is subjected to thorough testing under diverse conditions including process, voltage, temperature (PVT) fluctuations, and load variations, validating its reliability and robustness.

An energy-efficient design of ternary SRAM using GNRFETs

ABSTRACT The primary requirement of internet-of-things (IoT) applications is to have an energy-efficient design that extends the battery life for long-term operation. To achieve energy efficiency, one can employ multiple-valued logic (MVL) instead of binary logic and utilise graphene nanoribbon field-effect transistors (GNRFETs) as variable-threshold voltage (V th ) capable devices. The implementation of an MVL system enhances data transferability and reduces the number of interconnections, resulting in improved energy consumption compared to a binary system. In such systems, static random access memory (SRAM), which serves as a crucial component of very large-scale integrated (VLSI) chips, dominates energy consumption. This research paper introduces an energy-efficient ternary SRAM using GNRFETs. We propose a standard ternary inverter based on GNRFET devices, which serves as the fundamental building block of a storage cell. Simulation results conducted on a 32-nm GNRFET with a 0.9 V supply voltage demonstrate that the proposed design achieves energy consumption improvements ranging from 46.39% to 98.16% compared to the most recent ternary SRAMs. Furthermore, the SRAM cell is evaluated under various processes and environmental parameter variations.

Non-fourier phonon heat transport in graphene nanoribbon field effect transistors based on modified phonon hydrodynamic lattice Boltzmann method

Graphene, with its exceptional thermal conductivity and electron mobility, is widely recognized as a potential candidate for next-generation transistor materials. Despite the lack of pronounced phonon hydrodynamic phenomena at room temperature in graphene materials, momentum-conserving phonon normal scattering predominantly drives phonon hydrodynamic transport. Current methodologies, including the Single Mode Relaxation Time (SMRT) approximation and Fourier's law, inadequately capture phonon transport within the ballistic and hydrodynamic regimes of graphene. In light of these limitations, this study introduces a Non-gray phonon hydrodynamic lattice Boltzmann method in combination with the Temperature Jump Boundary Condition to provide a more accurate depiction of phonon heat transport in graphene nanoribbon field-effect transistors (GNRFETs) spanning these regimes. The findings reveal that our proposed model significantly mitigates heat transfer errors in GNRFETs, primarily driven by ballistic transport compared to the SMRT model. This suggests that the model's applicability extends beyond scenarios dominated by phonon hydrodynamics and is effective even in cases dominated by ballistic transport. In conclusion, our study emphasizes the impact of hydrodynamic transport on heat transfer in GNRFETs and underscores the importance of adjusting parameters related to the heating zone width and specular parameter to enhance thermal stability.

Reliable single-ended ultra-low power GNRFETs-based 9T SRAM cell with improved read and write operations

This paper presents a reliable single-ended nine-transistor (9T) static random access memory (SRAM) cell which is based on 16 nm graphene nanoribbon FETs (GNRFETs) technology. Single-ended operation significantly reduces switching activity and layout area. Therefore, the power consumption and area of the proposed cell is enhanced by 48.9 % and 3.8 %, respectively, as compared to the 2-bitline (2-BL) 9T SRAM cell. A separate read and write port provides significant improvement in the read and write performance simultaneously. The performance of the proposed cell and other existing cells are evaluated using HSPICE-simulations. The multi-threshold technology is used to improve the performance of cells in terms of delay and power consumption. The proposed cell shows significant improvement in read stability and write-ability due to proper device sizing ratio. In nanometer regime, the cell is capable to operate at ultra low supply voltage of 300 mV due to outstanding electrical property of the GNRFETs devices.

Graphene & its applications as field effect transistors

Graphene, owing to its excellent physical, mechanical, and electrical properties, as well as its outstanding optoelectronic properties, has garnered significant attention. Consequently, it has opened numerous opportunities for various types of future devices and systems. Graphene, a one-atom-thick layer of carbon atoms forming a honeycomb 2D crystal lattice, stands out as one of the most promising candidates in the field of nano- and microelectronics. This review provides an introduction to graphene, detailing its properties and its applications, particularly focusing on its utilization in the realm of Field Effect Transistors (FETs). Specifically, an analytical device model of heterostructure-based FETs is presented, which essentially comprises an array of nano ribbons clad. The model for Graphene Nano Ribbon (GNR) FETs includes Poisson's equation and can be employed to calculate the current-voltage characteristics and spatial distribution of electric potential along the channel.

Characterisation of graphene nano-ribbon field effect transistor and design of high performance PPN 12T GNRFET Full adder

Owing to the balanced electrical properties of graphene nanoribbon field effect transistors (GNRFETs), they are suitable next-generation devices for designing high performance circuits. However, as the fabrication for GNRFETs is at premature stage the performance of GNRFET device need to be explored with variation in its parameters. This article comprehensively analyses the impact of variations in GNRFET parameters on its threshold voltage, subthreshold swing and I ON /I OFF ratio. As an application example high performance PPN 12 T full adder is proposed using GNRFET device. The proposed full adder circuit shows dynamic power, propagation delay, low power-delay product and unity noise gain of 43.3 nW, 0.47 pS, 0.02 × 10−18 J and 0.46 respectively using supply voltage of 0.7 V. The performance of proposed full adder is compared with five previously proposed full adders using 16 nm GNRFET model in HSPICE simulation tool. Further, the impact of the GNRFET parameters on performance of proposed FA is investigated. A study of this nature is expected to improve performance of computing systems used in internet of things (IoT)-based infrastructure and health industry which demand for high performance next generation devices-based circuits.

ELECTRON TRANSPORT IN GRAPHENE BASED NANOTRANSISTOR AND USE OF NEGATIVE CAPACITANCE FOR STEEPER SUB-THRESHOLD SLOPE

Graphene has demonstrated tremendous promise in recent years as a material that, in the future, could replace silicon-based materials because of its exceptional electrical transfer characteristics. The diffusive MOSFETs suffer from short channel effects caused by their shorter channels, however graphene has numerous unusual features. The strongest material yet tested, Graphene exhibits a significant and nonlinear diamagnetism, has great mobility at room temperature, a low atomic thickness, a high current density, and is almost transparent. A single sheet of carbon atoms organized in a hexagonal lattice makes up graphene, an allotrope form of carbon. It is a semimetal with little short channel effects overall and little overlap between the valence and conduction bands. The Graphene nanoribbon has been incorporated into the ballistic nanotransistor as its channel and differentiate it form the diffusive one.In this review , I have presented the report on the survey of Nanotransistor . It has been divided into three sections : (1) Ballistic transport in Nanotransistor (2) Modelling of GNRFET (Graphene Nano-ribbon FET) using NEGF (Non-equilibrium Greens function) (3) Using ferroelectric capacitance into FET to reduce its sub-threshold regime below 60 mV/decade.The purpose of this review is to understand charge carrier transport phenomenon in the Nanotransistor. This includes the description about the ballistic nanotransister and differentiate it form the diffusive one. The NEGF allows us to characterizing its transfer characteristics in the real lattice space.Also the Id-Vd, sub-threshold regime , log(Id)-Vg , transmission coefficient and their application to drastically enhance the device performance for low energy digital electronics are being studied and modeled. Furthermore, the negative capacitance due to FE (ferroelectric layer) in FET will enhance the switching speed of FET and reduce the sub-threshold swing (SS) below 60 mV/decade which is impossible in case of traditional MOSFET. Thus, improving ION/IOFF ratio for low power digital devices.

An unbalanced ternary multiplier cell based on graphene nanoribbon field-effect transistors for PVT-tolerant low-energy portable applications

The potential benefits of using multiple-valued logic (MVL), especially ternary logic, which includes less interconnections, quicker response times, and smaller chip sizes, has gained the interest of designers of digital systems. A practical solution for achieving circuits with multiple thresholds in an efficient manner is through using graphene nanoribbon field-effect transistors (GNRFETs) that have modifiable threshold voltage values by adjusting the width of graphene nanoribbon. This article leverages the unique characteristics of GNRFETs and proposes a new design for a single-trit ternary multiplier (TMUL) circuit. The proposed TMUL uses two supply voltages to block direct current paths from high-to-low voltage levels, resulting in power and energy savings. Additionally, unary operators such as negative and positive ternary inverters and the complement of decisive literal are used to reduce transistor count and improve circuit performance. To thoroughly evaluate the performance of the proposed GNRFET-based TMUL circuit, extensive simulations are performed using Synopsis HSPICE tool and 32-nm channel length GNRFET devices, while taking into account the influences of process-voltage-temperature variations (PVT). The simulation results confirm the robustness and reliability of the proposed design, exhibiting reductions in power consumption by 71.18% to 76.36%, and energy consumption by 67.78% to 86.54%, when compared to other state-of-the-art TMUL circuits available in literature. Moreover, Monte-Carlo simulations have been performed to demonstrate that the suggested design exhibits reduced sensitivity towards significant process variations. As a result, the presented TMUL design can be a good choice for use in low-energy battery-operated portable multimedia device.

The understanding of the impact of efficiently optimized underlap length on analog/RF performance parameters of GNR-FETs

The aim of this study is to examine the analog/RF performance characteristics of graphene nanoribbon (GNR) field-effect transistors (FETs) using a novel technique called underlap engineering. The study employs self-consistent atomistic simulations and the non-equilibrium Green's function (NEGF) formalism. Initially, the optimal underlap length for the GNR-FET by device has been determined evaluating the ON-current (ION) to OFF-current (IOFF) ratio, which is a critical parameter for digital applications. Subsequently, the impact of underlap engineering on analog/RF performance metrics has been analyzed and conducting a comprehensive trade-off analysis considering parameters such as intrinsic-gain, transistor efficiency, and device cut-off frequency. The results demonstrate that the device incorporating the underlap mechanism exhibits superior performance in terms of the ION/IOFF ratio, transconductance generation factor (TGF), output resistance (r0), intrinsic gain (gmr0), gain frequency product (GFP), and gain transfer frequency product (GTFP). However, the device without the underlap effect demonstrates the highest transconductance (gm) and cut-off frequency (fT). Finally, a linearity analysis has been conducted to compare the optimized GNR-FET device with the conventional GNR-FET device without the underlap effect.

Investigation of Single-Event Upset in Graphene Nano-Ribbon FET SRAM Cell.

In recent years, graphene has received so much attention because of its superlative properties and its potential to revolutionize electronics, especially in VLSI. This study analyzes the effect of single-event upset (SEU) in an SRAM cell, which employs a metal-oxide semiconductor type graphene nano-ribbon field effect transistor (MOS-GNRFET) and compares the results with another SRAM cell designed using a PTM 10 nm FinFET node. Our simulations show that there is a change in the data stored in the SRAM after a heavy ion strike. However, it recovers from radiation effects after 0.46 ns for GNRFET and 0.51 ns for FinFET. Since the degradation observed in Q and Qb of GNRFET SRAM are 2.7X and 2.16X as compared to PTM nano-MOSFET, we can conclude that GNRFET is less robust to single effect upset. In addition, the stability of SRAM is improved by increasing the supply voltage VDD.

High-performance ternary designs using graphene nanoribbon transistors

Considering the issues emerging because of shrinking silicon field effect transistors (FETs), various post-silicon, post-binary logics are investigated by the researchers. The design of ternary schematics utilizing graphene nanoribbon FET (GNRFET) circuits is one alternate option. Since different threshold voltages are obtained by employing GNRFETs by varying its physical dimension, GNRFET is an ideal option for designing ternary circuits. The ternary circuit designs such as adder, subtractor and multiplier using GNRFETs are proposed in this study. These designs are developed using the ternary based decoder circuit. The proposed circuits are developed and executed in Synopsys based HSPICE simulator for functional verification. Additionally, the performances such as delay, power, power-delay-product (PDP) and energy-delay-product (EDP) of the proposed circuits are investigated and compared to CNTFET based ternary designs. The GNRFET ternary designs improved the performance on an average up to 30.96% than the CNTFET based designs.

An efficient GNRFET-based circuit design of ternary half-adder

Attaining low energy consumption in digital circuits design is a main task for designers because emerging applications are based on batteries and face limited-energy. Designing digital circuits with application to multiple-valued logic (MVL) and graphene nanoribbon field-effect transistor (GNRFET) provides a huge improvement in energy consumption. In this regard, this paper presents a novel ternary Half-Adder (THA) implemented with metal-oxide semiconductor (MOS)-type GNRFET. In the proposed THA, the Sum circuit is based on a combination of 3:1 ternary multiplexer, unary operators, and two supply voltages (dual-VDD), and the Carry circuit is based on unary operators, pass-transistor logic, and dual-VDD. The proposed THA is simulated using the 32-nm MOS-type GNRFET technology node at 0.9 V supply voltage in the HSPICE simulator. The proposed THA reduces the transistors count by 5.71–26.67% compared to the previously published THA circuits available in the literature, which are similar to the proposed THA from the design approach point of view. It is concluded from the simulation results that the proposed THA improves the power and energy consumptions by 83.33–91.41% and 66.38–82.27%, respectively. Moreover, the proposed THA is also designed and simulated using the Stanford 32-nm carbon nanotube field-effect transistor (CNTFET) technology. The proposed MOS-type GNRFET-based THA reduces the power and energy consumptions by 84.79% and 68.03%, respectively, and increases the delay by 2.12 × compared to its CNTFET-based counterpart. Moreover, the proposed CNTFET-based THA offers the second-lowest delay and power and the third-lowest energy compared to other existing CNTFET-based THA circuits.

High performance quaternary logic designs using GNFETs

The implementations of quaternary circuit schematics are presented in this paper. The quaternary logic is a better choice over the conventional logics because it offers high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented to design quaternary schematics using graphene nanoribbon field effect transistors (GNFETs). The dimer line of graphene nanoribbon (GN) is used to control the threshold voltage of GNFETs. Four quaternary logic inverter circuits such as standard quaternary inverter (SQI), intermediate quaternary inverter (IQI), positive quaternary inverter (PQI) and negative quaternary inverter (NQI) along with the NAND and NOR circuits are proposed. Furthermore, the quaternary half adder circuit is designed that helps to develop complex designs. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). The obtained circuit performances are compared with carbon nanotube FETs (CNFETs) based circuits. The comparison results show that the proposed GNFET circuits achieved 53.51% of overall performance improvement over the CNFET circuits.

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

SummaryInternet‐of‐Things (IoTs)‐based embedded systems require energy‐efficient designs for long‐term operation. To achieve energy‐efficient designs, multiple‐valued logic (MVL) circuits and graphene nanoribbon field‐effect transistors (GNRFETs) are used instead of binary logic circuits and complementary metal‐oxide‐semiconductor (CMOS), respectively. This paper presents a novel ultra‐low power and energy‐efficient ternary Half‐Adder (THA) circuit based on unary operators, two power supplies (dual‐VDD), VDD and VDD/2, and two ternary 3:1 multiplexers in 32 nm GNRFET technology. The superiority of the proposed design are improvements between 2.86% and 60% in transistor count, between 86.12% and 97.15% in power consumption, and between 58.14% and 98.39% in power‐delay‐product (PDP) compared to existing THA circuits. Moreover, the proposed THA circuit is also implemented with 32 nm carbon nanotube field‐effect transistors (CNTFETs). Simulation results indicate that the proposed GNRFET‐based THA circuit increases delay by 1.74 × and reduces power/PDP by 89.41%/81.63% compared to its CNTFET‐based counterpart.

Simultaneous Switching Noise Effects in Graphene-Based Power Distribution Networks

The simultaneous switching noise (SSN) effects in graphene nanoribbon field effect transistor (GNRFET) based ternary circuits are presented in this study. The performance in terms of SSN induced peak noise and propagation delay on power and ground rails are investigated in multilayer graphene nanoribbon (MLGNR) bundled power interconnects using Hewlett simulation program with integrated circuit emphasis (HSPICE) simulator. Furthermore, these investigations are compared to the copper (Cu) and multiwalled carbon nanotubes (MWCNT) based power interconnects. From the results, it is noticed that the proposed MLGNR interconnects shows performance improvements up to 74.9% and 33.8% over the Cu and MWCNT interconnects. Moreover, the SSN peak noise and delay are investigated for different interconnect lengths from 200 μm to 500 μm. It is observed that the SSN noise on power and ground rail is reduced and propagation delay is increased as interconnect length is increased.

Signal Integrity Assessment of GNRFET-Based Ternary Logic for Multi Layered GNR Interconnects with Dielectric Insertion

In this paper, signal integrity assessment is carried out for graphene nanoribbon field effect transistor (GNRFET) based ternary logic with dielectric inserted multi-layered GNR (MLGNR) interconnects. The analyses are carried out for crosstalk effects and eye diagrams with and without shielding lines. In this paper firstly, it is observed that the dielectric inserted MLGNR interconnects show better than copper (Cu) and multiwall carbon nanotube (MWCNT) interconnects. Secondly, active shield technique is adopted, and observed that it exhibits better performance than without shield and passive shield techniques. Also, the power-delay product performance parameter is evaluated and envisaged that active shield technique outperforms passive technique. Further, the eye diagram analysis is carried out for different bit rates. The different performance analyses in the paper have been carried out for 10 nm technology node.

Graphene Nanoribbon Field Effect Transistor Simulations for the Detection of Sugar Molecules: Semi-Empirical Modeling

Graphene has remarkable characteristics that make it a potential candidate for optoelectronics and electronics applications. Graphene is a sensitive material that reacts to any physical variation in its environment. Due to its extremely low intrinsic electrical noise, graphene can detect even a single molecule in its proximity. This feature makes graphene a potential candidate for identifying a wide range of organic and inorganic compounds. Graphene and its derivatives are considered one of the best materials to detect sugar molecules due to their electronic properties. Graphene has low intrinsic noise, making it an ideal membrane for detecting low concentrations of sugar molecules. In this work, a graphene nanoribbon field effect transistor (GNR-FET) is designed and utilized to identify sugar molecules such as fructose, xylose, and glucose. The variation in the current of the GNR-FET in the presence of each of the sugar molecules is utilized as the detection signal. The designed GNR-FET shows a clear change in the device density of states, transmission spectrum, and current in the presence of each of the sugar molecules. The simulated sensor is made of a pair of metallic zigzag graphene nanoribbons (ZGNR) joint via a channel of armchair graphene nanoribbon (AGNR) and a gate. The Quantumwise Atomistix Toolkit (ATK) is used to design and conduct the nanoscale simulations of the GNR-FET. Semi-empirical modeling, along with non-equilibrium Green's functional theory (SE + NEGF), is used to develop and study the designed sensor. This article suggests that the designed GNR transistor has the potential to identify each of the sugar molecules in real time with high accuracy.

Controlled Preparation and Device Application of Sub-5 nm Graphene Nanoribbons and Graphene Nanoribbon/Carbon Nanotube Intramolecular Heterostructures

Narrow graphene nanoribbons (GNRs) and GNR/single-walled carbon nanotube (SWNT) intramolecular heterojunctions are ideal candidates to construct next-generation electronic and optoelectronic devices. However, the fabrication of high-quality long sub-5 nm wide GNRs and GNR/SWNT heterojunctions is a great challenge. Here, we report a method to produce high-quality sub-5 nm wide GNRs with smooth edges and GNR/SWNT intramolecular heterostructures via palladium-catalyzed full and partial unzipping of SWNTs, respectively. The resulting GNRs could be as narrow as 2.2 nm and had an average length of over 1 μm. By adjusting the unzipping time and the deposited positions of palladium nanoparticles, controlled multiple GNR/SWNT heterostructures were also fabricated on an individual parent SWNT. A GNR field-effect transistor (FET) constructed by a 3.1 nm wide GNR could simultaneously achieve a high on/off current ratio of 1.1 × 104 and a large mobility of 598 cm2 V-1 s-1. The photovoltaic device based on a single GNR (2.4 nm in width)/SWNT (0.8 nm in diameter) heterojunction exhibited a large open-circuit voltage (Voc) of 0.52 V and a high external power conversion efficiency (η) of 4.7% under the 1550 nm wavelength illumination of 931 mW cm-2. Our method provides a pathway to controllably prepare high-quality sub-5 nm GNRs and GNR/SWNT heterojunctions for fundamental studies and practical applications in the electronic and optoelectronic fields.

Effects of passivation type on electrical transport of a defect-engineered graphene nanoribbon FET

Effects of passivation type on electrical transport of a defect-engineered graphene nanoribbon FET