Graphene Nanoribbon Field-effect Transistors Research Articles

Performance Evaluation and Optimization of Triple Cascode Operational Transconductance Amplifiers Using GNRFET Technology for Low Power Smart Devices

Abstract Abstract: Front-end circuits are crucial interfaces between digital electronics and real-world applications in Internet-of-Things (IoT) systems and portable smart devices, necessitating high-speed, energy-efficient, and compact designs. Advanced mixed-signal processing and actuation technologies are essential for leveraging the pivotal role of analog sensors in Artificial Intelligence (AI) functionalities. This study investigates emerging low-power nanoelectronics for analog circuit applications, focusing on Graphene Nano-ribbon Field-Effect Transistors (GNRFETs), particularly one-dimensional armchair graphene nanoribbons (AGNRs). Triple cascode operational transconductance amplifiers (TCOTAs) are implemented using GNRFETs and MOSFETs at the 32-nanometer technology node using HSPICE. Three distinct GNR-based TCOTA configurations are analyzed against conventional CMOS-based TCOTA to assess performance improvements. The evaluation highlights significant enhancements in GNR-based TCOTAs, particularly in the pure GNRFET-TCOTA variant, which exhibits a notable 33.8% increase in DC gain, a 21.4% improvement in common-mode rejection ratio (CMRR), and substantial growth rates of 5.85 and 8.47 times for slew rate and 3-dB bandwidth, respectively. Compared to Si-CMOS-based TCOTA, the pure GNR-based TCOTA demonstrates a 9.4% reduction in delay and an energy-delay product (EDP) approximately 4% lower. Insights into critical design parameters such as dimer lines (N), number of GNRs (nRib), and ribbon spacing (WSP) are provided, emphasizing their impact on circuit performance. This research underscores the potential of GNRFET to optimize operational transconductance amplifiers, enhancing analog circuit capabilities for IoT systems and portable electronics. The findings contribute to advancing nanoelectronics toward achieving higher performance and efficiency in future electronic applications.

New Label-Free DNA Nanosensor Based on Top-Gated Metal-Ferroelectric-Metal Graphene Nanoribbon on Insulator Field-Effect Transistor: A Quantum Simulation Study.

In this paper, a new label-free DNA nanosensor based on a top-gated (TG) metal-ferroelectric-metal (MFM) graphene nanoribbon field-effect transistor (TG-MFM GNRFET) is proposed through a simulation approach. The DNA sensing principle is founded on the dielectric modulation concept. The computational method employed to evaluate the proposed nanobiosensor relies on the coupled solutions of a rigorous quantum simulation with the Landau-Khalatnikov equation, considering ballistic transport conditions. The investigation analyzes the effects of DNA molecules on nanodevice behavior, encompassing potential distribution, ferroelectric-induced gate voltage amplification, transfer characteristics, subthreshold swing, and current ratio. It has been observed that the feature of ferroelectric-induced gate voltage amplification using the integrated MFM structure can significantly enhance the biosensor's sensitivity to DNA molecules, whether in terms of threshold voltage shift or drain current variation. Additionally, we propose the current ratio as a sensing metric due to its ability to consider all DNA-induced modulations of electrical parameters, specifically the increase in on-state current and the decrease in off-state current and subthreshold swing. The obtained results indicate that the proposed negative-capacitance GNRFET-based DNA nanosensor could be considered an intriguing option for advanced point-of-care testing.

Analysis on density of states and ION/IOFF ratio of GaN/GaN-graphene nanoribbon tunnel FET for enhanced bio-sensing applications

Abstract This research introduces a new analytical model that studies the effect of ferro-dielectric on the operational performance of TFETs doped with halogens. The effect of source and drain depletions, voltage-drain & gate, thickness and capacitance of gate insulator are all investigated in this study. Accurate measurements of the surface potential are required to ascertain the transconductance, gate-to-drain capacitance, and lateral electric field of the device. Our model, which employs Ferroelectric Halo-Doped double gate (FHDD)-gated device designs, has been demonstrated to produce results that nearly match those produced from TCAD simulations. This was accomplished by doing a comparative analysis of the outcomes derived from both sets of simulations. Furthermore, the performance of the suggested structure of TFET, which integrates a dielectric of Fe and GaN heterostructure, surpasses that of other similar devices (fT) in terms of ON current, ON/OFF ratio, transconductance, and cut-off frequency. A ferroelectric dielectric was used to create a ferroelectric heterostructure. This study also centers on the creation and application of a graphene nanoribbon field effect transistor (GNR-TFET) to detect sugar molecules, specifically fructose, xylose, and glucose. The detecting signal is generated by utilizing the fluctuation in the electrical current of the GNR-TFET caused by the presence of individual sugar molecules. The GNR-TFET exhibits noticeable variations in the density of states, transmission spectrum, and current when exposed to individual sugar molecules. The sensor under investigation is being developed and examined using a combination of semi-empirical modeling and non-equilibrium Green's functional theory (SE + NEGF). According to the research, the modified GNR TFET has the ability to quickly and accurately detect individual sugar molecules in real-time.

Investigation of PNN Inverter-Based Low PDP 12T GNRFET Full Adder for VLSI Signal Processing Applications

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16[Formula: see text]nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16[Formula: see text]nm MOS-GNRFET model.

Graphene nanoribbon FET technology‐based OTA for optimizing fast and energy‐efficient electronics for IoT application: Next‐generation circuit design

AbstractThe Internet of Things (IoT) and portable electronic devices are pivotal in enhancing living standards, with battery efficiency and compact design being critical for these devices. Analogue sensors, integral to advanced artificial intelligence, often necessitate complex real‐time processing and actuation. This study examines the performance of one‐dimensional armchair graphene nanoribbons in graphene nanoribbon field‐effect transistors (GNRFETs). It compares graphene nanoribbon‐based triple cascode operational transconductance amplifiers (GNRFET‐TCOTAs) with conventional CMOS‐based TCOTA. The results reveal substantial enhancements in the GNRFET‐based TCOTAs: the pure GNR‐TCOTA variant shows a remarkable 33.8% increase in DC gain and significant improvements in transconductance, slew rate, and gain‐bandwidth, with enhancements of 8.48, 5.85, and 8.56 times, respectively. Furthermore, the pure GNRFET TCOTA exhibits higher speed, lower energy‐delay product, and settling time compared to Si‐CMOS‐based TCOTA. The study also investigates the impact of critical design parameters on circuit performance. Overall, the research highlights the potential of GNRFETs to optimize TCOTA circuits, offering a path towards more efficient and compact electronic devices, thereby advancing the state of nanoelectronics and supporting the growth of high‐performance IoT systems.

A simulation study of electrostatically doped silicene and graphene nanoribbon FETs

A simulation study of electrostatically doped silicene and graphene nanoribbon FETs

A comprehensive analysis of ultra low power GNRFET based 20T hybrid full adder for computing applications

In an era where energy efficiency is as important as computational speed, this paper introduces a new full adder circuit design that effectively integrates dynamic power gathering (DPG) power conservation benefits with XOR-XNOR pass-transistor logic (PTL) area and performance efficiencies using graphene nanoribbon field-effect transistors. GNRFETs are useful for digital logic due to their high carrier mobility and tunable bandgap. The paper describes the circuit’s seamless transition full adder response, demonstrating the tri-mode dynamic power gating strategy capacity to reduce static power depletion. The proposed hybrid full adder performs well with 7.76 nW power consumption, 481 ps latency, and 3.73 aJ PDP. This reduces power consumption by 99.9%, delay by 99.0%, and PDP by 99.8% compared to other adders. The effects of temperature, voltage, Noise immunity and Carry Forward Adders integration on power, delay, and PDP are also analysed, proving the design’s robustness. The adaptability of our full adder architecture allows its implementation in more complicated arithmetic and logic units, indicating a scalable and energy-efficient paradigm for future integrated circuits.

H/O edge passivated B/N co-doped armchair graphene nanoribbon field-effect transistors, based on first principles

This study employs the nonequilibrium Green’s function method in conjunction with density functional theory to fabricate and analyze a Graphene Nanoribbon Field-Effect Transistor (GNRFET). The co-doping of B and N creates built-in electric fields, thereby reducing leakage current. The results demonstrate effective control performance of planar gates, as evidenced by an increase in IDS with rising gate voltage. Furthermore, a negative differential conductance phenomenon is observed at bias voltages exceeding 0.7 V, exhibiting correlation with transmission spectra and energy band structures. To precisely illustrate the electron distribution within the doped scattering region, calculations involving transport paths, the molecular projection self-consistent Hamiltonian (MPSH), and the emission eigenvalues and eigenstates of the device are conducted. This research provides a reference for exploring and developing smaller and more energy-efficient AGNR field effect transistor designs and implementations. The principal objective of this paper is to investigate the potential applications of these smaller, more energy-efficient devices.

Design and Simulation of New High Speed, Low Power D-Flip-Flops, Implemented Using Graphene Nanoribbon and Carbon Nanotube Field Effect Transistors

Design and Simulation of New High Speed, Low Power D-Flip-Flops, Implemented Using Graphene Nanoribbon and Carbon Nanotube Field Effect Transistors

Area-energy optimized ternary multiplier usingefficient design approaches in GNRFET technology

The semiconductor industry has long benefited from CMOS transistors in realizing advanced VLSI circuits. However, achieving area-energy optimization in CMOS-based VLSI circuits has become increasingly challenging due to short-channel effects. Another obstacle in manufacturing these transistors is the adoption of body-biasing techniques to adjust the threshold voltage (Vth) for developing ternary logic-based circuits. Researchers are now exploring emerging devices like graphene nanoribbon field-effect transistors (GNRFET) as potential candidates for future electronics. GNRFET devices not only leverage graphene’s remarkable properties but also benefit from the ability to achieve distinct Vth through tuning the width of graphene nanoribbons. This paper focuses on using tri-state 32-nm GNRFET devices to implement a novel area-energy optimized ternary multiplier circuit. To attain a logic ‘1′ in the proposed circuit, a power-efficient voltage division technique is employed. Additionally, efficient design approaches are used to reduce the critical path length and decrease the number of necessary transistors. Simulation results using HSPICE demonstrate that the proposed design reduces energy consumption by a minimum of 6.75% and up to 37.50% compared to other state-of-the-art 32-nm GNRFET-based TMUL circuits. Furthermore, the proposed design decreases both the area and complexity by utilizing a single-VDD and incorporating 24 transistors.

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

Tri-state GNRFET-based fast and energy-efficient ternary multiplier

As silicon field-effect transistors encounter increasing scaling challenges, digital system designers are shifting their attention towards multi-valued logic (MVL), specifically ternary logic. The graphene nanoribbon field-effect transistor (GNRFET) emerges as a compelling alternative among post-MOSFET technologies for the implementation of ternary logic. This paper delves into the computational intricacies of ternary logic, underscores the outstanding features of GNRFET technology, and introduces a novel GNRFET-based 1-trit ternary multiplier (TMUL) requiring only 26 transistors. The performance of the design is assessed using the Synopsis HSPICE simulator with a 32-nm GNRFET model file operating at VDD = 0.9 V. The proposed TMUL surpasses existing designs due to its efficient paths with a minimal number of transistors for each output transition, a singular power supply voltage, and an extended voltage division scheme. In comparison to other contemporary TMUL designs, the proposed design exhibits a notable enhancement, showcasing a 21.42 % reduction in delay, a 33.11 % decrease in power-delay-product (PDP), and a 58.17 % decrease in energy-delay-product (EDP). Additionally, the design is subjected to thorough testing under diverse conditions including process, voltage, temperature (PVT) fluctuations, and load variations, validating its reliability and robustness.

An energy-efficient design of ternary SRAM using GNRFETs

ABSTRACT The primary requirement of internet-of-things (IoT) applications is to have an energy-efficient design that extends the battery life for long-term operation. To achieve energy efficiency, one can employ multiple-valued logic (MVL) instead of binary logic and utilise graphene nanoribbon field-effect transistors (GNRFETs) as variable-threshold voltage (V th ) capable devices. The implementation of an MVL system enhances data transferability and reduces the number of interconnections, resulting in improved energy consumption compared to a binary system. In such systems, static random access memory (SRAM), which serves as a crucial component of very large-scale integrated (VLSI) chips, dominates energy consumption. This research paper introduces an energy-efficient ternary SRAM using GNRFETs. We propose a standard ternary inverter based on GNRFET devices, which serves as the fundamental building block of a storage cell. Simulation results conducted on a 32-nm GNRFET with a 0.9 V supply voltage demonstrate that the proposed design achieves energy consumption improvements ranging from 46.39% to 98.16% compared to the most recent ternary SRAMs. Furthermore, the SRAM cell is evaluated under various processes and environmental parameter variations.

Non-fourier phonon heat transport in graphene nanoribbon field effect transistors based on modified phonon hydrodynamic lattice Boltzmann method

Graphene, with its exceptional thermal conductivity and electron mobility, is widely recognized as a potential candidate for next-generation transistor materials. Despite the lack of pronounced phonon hydrodynamic phenomena at room temperature in graphene materials, momentum-conserving phonon normal scattering predominantly drives phonon hydrodynamic transport. Current methodologies, including the Single Mode Relaxation Time (SMRT) approximation and Fourier's law, inadequately capture phonon transport within the ballistic and hydrodynamic regimes of graphene. In light of these limitations, this study introduces a Non-gray phonon hydrodynamic lattice Boltzmann method in combination with the Temperature Jump Boundary Condition to provide a more accurate depiction of phonon heat transport in graphene nanoribbon field-effect transistors (GNRFETs) spanning these regimes. The findings reveal that our proposed model significantly mitigates heat transfer errors in GNRFETs, primarily driven by ballistic transport compared to the SMRT model. This suggests that the model's applicability extends beyond scenarios dominated by phonon hydrodynamics and is effective even in cases dominated by ballistic transport. In conclusion, our study emphasizes the impact of hydrodynamic transport on heat transfer in GNRFETs and underscores the importance of adjusting parameters related to the heating zone width and specular parameter to enhance thermal stability.

Reliable single-ended ultra-low power GNRFETs-based 9T SRAM cell with improved read and write operations

This paper presents a reliable single-ended nine-transistor (9T) static random access memory (SRAM) cell which is based on 16 nm graphene nanoribbon FETs (GNRFETs) technology. Single-ended operation significantly reduces switching activity and layout area. Therefore, the power consumption and area of the proposed cell is enhanced by 48.9 % and 3.8 %, respectively, as compared to the 2-bitline (2-BL) 9T SRAM cell. A separate read and write port provides significant improvement in the read and write performance simultaneously. The performance of the proposed cell and other existing cells are evaluated using HSPICE-simulations. The multi-threshold technology is used to improve the performance of cells in terms of delay and power consumption. The proposed cell shows significant improvement in read stability and write-ability due to proper device sizing ratio. In nanometer regime, the cell is capable to operate at ultra low supply voltage of 300 mV due to outstanding electrical property of the GNRFETs devices.

Graphene & its applications as field effect transistors

Graphene, owing to its excellent physical, mechanical, and electrical properties, as well as its outstanding optoelectronic properties, has garnered significant attention. Consequently, it has opened numerous opportunities for various types of future devices and systems. Graphene, a one-atom-thick layer of carbon atoms forming a honeycomb 2D crystal lattice, stands out as one of the most promising candidates in the field of nano- and microelectronics. This review provides an introduction to graphene, detailing its properties and its applications, particularly focusing on its utilization in the realm of Field Effect Transistors (FETs). Specifically, an analytical device model of heterostructure-based FETs is presented, which essentially comprises an array of nano ribbons clad. The model for Graphene Nano Ribbon (GNR) FETs includes Poisson's equation and can be employed to calculate the current-voltage characteristics and spatial distribution of electric potential along the channel.

Characterisation of graphene nano-ribbon field effect transistor and design of high performance PPN 12T GNRFET Full adder

Owing to the balanced electrical properties of graphene nanoribbon field effect transistors (GNRFETs), they are suitable next-generation devices for designing high performance circuits. However, as the fabrication for GNRFETs is at premature stage the performance of GNRFET device need to be explored with variation in its parameters. This article comprehensively analyses the impact of variations in GNRFET parameters on its threshold voltage, subthreshold swing and I ON /I OFF ratio. As an application example high performance PPN 12 T full adder is proposed using GNRFET device. The proposed full adder circuit shows dynamic power, propagation delay, low power-delay product and unity noise gain of 43.3 nW, 0.47 pS, 0.02 × 10−18 J and 0.46 respectively using supply voltage of 0.7 V. The performance of proposed full adder is compared with five previously proposed full adders using 16 nm GNRFET model in HSPICE simulation tool. Further, the impact of the GNRFET parameters on performance of proposed FA is investigated. A study of this nature is expected to improve performance of computing systems used in internet of things (IoT)-based infrastructure and health industry which demand for high performance next generation devices-based circuits.

ELECTRON TRANSPORT IN GRAPHENE BASED NANOTRANSISTOR AND USE OF NEGATIVE CAPACITANCE FOR STEEPER SUB-THRESHOLD SLOPE

Graphene has demonstrated tremendous promise in recent years as a material that, in the future, could replace silicon-based materials because of its exceptional electrical transfer characteristics. The diffusive MOSFETs suffer from short channel effects caused by their shorter channels, however graphene has numerous unusual features. The strongest material yet tested, Graphene exhibits a significant and nonlinear diamagnetism, has great mobility at room temperature, a low atomic thickness, a high current density, and is almost transparent. A single sheet of carbon atoms organized in a hexagonal lattice makes up graphene, an allotrope form of carbon. It is a semimetal with little short channel effects overall and little overlap between the valence and conduction bands. The Graphene nanoribbon has been incorporated into the ballistic nanotransistor as its channel and differentiate it form the diffusive one.In this review , I have presented the report on the survey of Nanotransistor . It has been divided into three sections : (1) Ballistic transport in Nanotransistor (2) Modelling of GNRFET (Graphene Nano-ribbon FET) using NEGF (Non-equilibrium Greens function) (3) Using ferroelectric capacitance into FET to reduce its sub-threshold regime below 60 mV/decade.The purpose of this review is to understand charge carrier transport phenomenon in the Nanotransistor. This includes the description about the ballistic nanotransister and differentiate it form the diffusive one. The NEGF allows us to characterizing its transfer characteristics in the real lattice space.Also the Id-Vd, sub-threshold regime , log(Id)-Vg , transmission coefficient and their application to drastically enhance the device performance for low energy digital electronics are being studied and modeled. Furthermore, the negative capacitance due to FE (ferroelectric layer) in FET will enhance the switching speed of FET and reduce the sub-threshold swing (SS) below 60 mV/decade which is impossible in case of traditional MOSFET. Thus, improving ION/IOFF ratio for low power digital devices.

An unbalanced ternary multiplier cell based on graphene nanoribbon field-effect transistors for PVT-tolerant low-energy portable applications

The potential benefits of using multiple-valued logic (MVL), especially ternary logic, which includes less interconnections, quicker response times, and smaller chip sizes, has gained the interest of designers of digital systems. A practical solution for achieving circuits with multiple thresholds in an efficient manner is through using graphene nanoribbon field-effect transistors (GNRFETs) that have modifiable threshold voltage values by adjusting the width of graphene nanoribbon. This article leverages the unique characteristics of GNRFETs and proposes a new design for a single-trit ternary multiplier (TMUL) circuit. The proposed TMUL uses two supply voltages to block direct current paths from high-to-low voltage levels, resulting in power and energy savings. Additionally, unary operators such as negative and positive ternary inverters and the complement of decisive literal are used to reduce transistor count and improve circuit performance. To thoroughly evaluate the performance of the proposed GNRFET-based TMUL circuit, extensive simulations are performed using Synopsis HSPICE tool and 32-nm channel length GNRFET devices, while taking into account the influences of process-voltage-temperature variations (PVT). The simulation results confirm the robustness and reliability of the proposed design, exhibiting reductions in power consumption by 71.18% to 76.36%, and energy consumption by 67.78% to 86.54%, when compared to other state-of-the-art TMUL circuits available in literature. Moreover, Monte-Carlo simulations have been performed to demonstrate that the suggested design exhibits reduced sensitivity towards significant process variations. As a result, the presented TMUL design can be a good choice for use in low-energy battery-operated portable multimedia device.

The understanding of the impact of efficiently optimized underlap length on analog/RF performance parameters of GNR-FETs

The aim of this study is to examine the analog/RF performance characteristics of graphene nanoribbon (GNR) field-effect transistors (FETs) using a novel technique called underlap engineering. The study employs self-consistent atomistic simulations and the non-equilibrium Green's function (NEGF) formalism. Initially, the optimal underlap length for the GNR-FET by device has been determined evaluating the ON-current (ION) to OFF-current (IOFF) ratio, which is a critical parameter for digital applications. Subsequently, the impact of underlap engineering on analog/RF performance metrics has been analyzed and conducting a comprehensive trade-off analysis considering parameters such as intrinsic-gain, transistor efficiency, and device cut-off frequency. The results demonstrate that the device incorporating the underlap mechanism exhibits superior performance in terms of the ION/IOFF ratio, transconductance generation factor (TGF), output resistance (r0), intrinsic gain (gmr0), gain frequency product (GFP), and gain transfer frequency product (GTFP). However, the device without the underlap effect demonstrates the highest transconductance (gm) and cut-off frequency (fT). Finally, a linearity analysis has been conducted to compare the optimized GNR-FET device with the conventional GNR-FET device without the underlap effect.