Polycrystalline Silicon Grain Research Articles

Influence of dislocations on photovoltaic properties of multicrystalline silicon solar cells

expdrimentaux. Abstract. The photovoltaic properties of large grained polycrystalline silicon solar cells are mainly affected by the presence of dislocations. Both the recombination of carriers at dislocation (which degrades the photocurrent) and the transport of carriers along the dislocation cores crossing the junction (which increases the dark current) are taken into account. The influence of the density N~~, and recombination activity S~ of dislocations on the short circuit current density J~~, open circuit voltage V~~, fill factor FF, and efficiency 1~ are computed. The computed values are compared to experimental results.

Anomalous capacitance-voltage behavior due to dopant segregation and carrier trapping in As-implanted polycrystalline silicon and silicided polycrystalline silicon gates

This letter discusses the anomalous capacitance-voltage characteristics of As-implanted polycrystalline silicon and amorphous Si gate metal-oxide-semiconductor (MOS) structures fabricated with and without a TiSi2 layer. The effects of gate bias and process parameters such as annealing temperature, process details of silicide formation, and polycrystalline silicon grain microstructure on the capacitance-voltage (C-V) characteristics have also been studied. It is shown that insufficient As redistribution at 800 °C, coupled with carrier trapping at polycrystalline silicon grain boundaries and dopant segregation in TiSi2, causes depletion effects in the polycrystalline silicon gate and in turn, the anomalous C-V behavior. The depletion tends to increase the ‘‘effective’’ gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (≥900 °C) are sufficient to achieve degenerate doping in the polycrystalline silicon gates and avoid the depletion effects.

Tunneling barrier height imaging and polycrystalline Si surface observations

An influence of the dopant concentration on polycrystalline Si grain structure, electronic structure and dopant segregation in 800 °C and 30 min annealing is investigated. Barrier height images and topographies of arsenic implanted polycrystalline silicon surface are obtained using tunneling barrier height imaging (TBI) and scanning tunneling microscopy (STM) with the vacuum pressure less than 5×10−7 Torr. As results, a conduction band bending caused by the arsenic ion implantation can be observed by the TBI. A comparison of the TBI image with the STM image can identify whether region is implanted or nonimplanted. In addition, dopant segregation structures at the grain boundary can be found out. With dopant concentration, 1014 cm−2 As+ implanted polycrystalline silicon grain structures of 4–80 nm size grow large.

Influence of dislocations on electrical properties of large grained polycrystalline silicon cells. II. Experimental results

The predictions of the model given in part I are tested by means of a set of diode arrays which allow us to measure the electron effective diffusion length (Leff) and the short circuit photocurrent (Jsc) in large grained polycrystalline silicon cells. The experimental dependencies of Leff and Jsc on the average of the dislocation density (Ndis) fit well with the computed curves, and then the mean value of the recombination strength of dislocations (Sd) may be evaluated. As predicted by the model, the reduction of the value of Sd by a passivation technique like hydrogenation, significantly increases the values of Leff and Jsc. The good agreement between computed and experimental results indicate that dislocations are the most harmful defects.

Influence of dislocations on electrical properties of large grained polycrystalline silicon cells. I. Model

The influence of the density (Ndis) and of the recombination activity (Sd) of dislocations on the photocurrent (Jsc), the spectral dependence of Jsc and the effective electron diffusion length (Leff) of a P+-N junction solar cell are computed by means of a model which makes use of the Green’s function method. In this model Sd is the surface recombination velocity of the space-charge cylinder surrounding the dislocation line and the dislocations are assumed to be perpendicular to the illuminated surface of the cells and homogeneously recombining. The results obtained indicate that the values of Jsc and their spectral variations, as well as values of Leff, are dependent on both Ndis and Sd, especially when Ndis and Sd are larger than 103 cm−2 and 104 cm s−1, respectively. The base thickness (d) of the cells and the value of electron diffusion length (Ln) in the undislocated regions of the wafers are also introduced in the model as independent parameters.

Formation of polycrystalline silicon grains in Si+-preamorphized, BF+2-implanted (111)Si

The regrowth of Si+-preamorphized and BF+2- implanted thin films on (111)Si has been studied by both plan-view and cross-sectional transmission electron microscopy. Polycrystalline Si grains were found to form in Si+-preamorphized and BF+2- implanted (111)Si with the original amorphous-crystalline (a-c) interface located deeper in the preamorphized Si substrate than in BF+2- implanted samples. Rapid thermal annealing was performed to obtain kinetic data for the formation of polycrystalline Si grains. The nucleation and growth of polycrystalline Si grains were found to occur in the amorphous phase ahead of the growing a-c interface. The incubation time for the formation of 4 nm or larger crystallites in amorphous Si at 700 °C was found to be less than 30 s. The results are discussed in terms of the competition between the propagation of the a-c interface to sweep over the potential nucleation sites and random nucleation in the amorphous phase. Ramifications of the formation of polycrystalline Si grains in instances with a relatively low ion dosage and/or moderate annealing temperature are addressed.

Dopant Segregation at Polycrystalline Silicon Grain Boundaries in Device Fabrication Processes

AbstractThe dopant segregation at the polycrystalline silicon grain boundaries in device fabrication processes has been studied with a new approach using spreading resistance(SR) measurement, SIMS and cross-sectional TEM(XTEM). Phosphorus implanted LPCVD poly-Si films were annealed at 900°C-1000°C in N2 for 30min. Electrically active dopant concentrations obtained from SR measurements are constant in depth within the poly-Si films. On the other hand, the phosphorus concentration measured by SIMS is found to increase with increasing depth and to have linear relationships to reciprocal grain sizes observed by XTEM for all poly-Si films. The linear relationship indicates that the number of segregated phosphorus atoms per unit grain surface area at the grain boundaries is uniform throughout poly-Si films. Both phosphorus concentrations in the grains and at the grain boundaries are evaluated. The heat of segregation of 1.7eV is obtained from the annealing temperature dependence of the segregation ratio. Our results indicate that carrier concentration in the poly-Si film is more sensitive to annealing temperature in device fabrication processes. The carries concentration is determined by kinetics rather than by equilibrium segregation of dopants.

Polycrystalline Silicon Emitter Contacts Formed by Rapid Thermal Annealing

The effect of rapid thermal annealing on the formation of polycrystalline silicon/interfacial oxide/single crystal silicon emitters is examined. The emitter width, defined as the distance from the oxide to the emitter junction, and the base width, defined as the distance from the emitter to the base junction, are measured by secondary ion mass spectrometry and spreading resistance depth profiling, thus differentiating between metallurgical and electrical junctions. Under isochronal annealing conditions of 10s, the metallurgically‐electrically equivalent emitter width increases monotonically from 0.04 μm at 900°C to 0.11 μm at 1050°C. By contrast, the nominal 0.38 μm metallurgical and 0.14 μm electrical base widths are essentially invariant to temperature. Under isothermal annealing conditions of 1050° and 900°C, there is almost no dependence on time of the emitter and base widths from 1 to 10, and 10 to 30s, respectively. Arsenic diffuses out of the polycrystalline silicon under all annealing conditions, especially as the annealing temperature is raised, causing an increase in sheet resistance of the emitter that is partly proportional to the arsenic loss. High resolution transmission electron microscopy shows that the interfacial oxide layer is stable to at least 900°C with both the number and size of epitaxial protuberances increasing with temperature, but not with annealing time. At 1050°C the interfacial oxide layer agglomerates, and as a consequence, epitaxial realignment of the polycrystalline silicon grains with the single crystal substrate occurs. By comparison, 30 min furnace annealing at 950°C results in emitter and base widths of 0.10 and 0.30 μm, respectively. There is almost no loss of arsenic, and the emitter sheet resistance is almost three times lower, and the base pinch resistance is approximately four times higher than that obtained by any rapid thermal annealing cycle. The interfacial oxide, although bumpy, remains intact, thus preventing any epitaxial realignment from occurring.

Effect of post-oxidation anneal temperature on radiation-induced charge trapping in metal-oxide-semiconductor devices

Polycrystalline silicon-gate metal-oxide-semiconductor (MOS) capacitors have been fabricated with high-temperature anneals from 800 to 950 °C after gate oxidation and polycrystalline silicon deposition. Temperatures from 800 to 875 °C are found to have very little effect on the radiation response of these devices. However, a rapid increase in radiation-induced oxide-trapped charge, ΔVot, is observed for anneal temperatures above 875 °C. This increase in ΔVot coincides with an experimentally observed change in the polycrystalline silicon grain structure. The anneal temperature was found to have a much smaller effect on radiation-induced interface-trap charge. The correlation of these results to other properties, e.g., stress, is discussed.

Polysilicon Resistor Modification with Hydrogen Plasmas on Fabricated Integrated Circuits

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Subthreshold model of a polycrystalline silicon thin-film field-effect transistor

A model is presented for the subthreshold current versus gate voltage of a polycrystalline silicon thin-film field-effect transistor. It utilizes the experimentally observed exponential density of states of polycrystalline silicon grain boundaries and is based on an earlier model of M. Shur and M. Hack [J. Appl. Phys. 55, 3831 (1984)] which they applied to hydrogenated amorphous silicon. Experimental subthreshold curves are presented along with the corresponding curves predicted by the model. In addition current activation data are shown to fit the model. The primary fitting parameter is the density of states at the valence band.

Influence of the Decoration by Dislocations on Grain Boundary Passivation by Hydrogen in Silicon

ABSTRACTIn large grained polycrystalline silicon, the recombination activity of G.B.'s and their passivation by hydrogen is found to be dependent on the decoration by dislocations. Dislocations appear to be preferential paths for in-diffusion, at a depth of a few hundreds of pim's. Similar enhancements of diffusion and passivation exist in grains around dislocations.

Improvement of electron diffusion lengths in polycrystalline silicon wafers by aluminium

In order to improve the electron diffusion lengths Ln in P-type large grained polycrystalline silicon wafers, an aluminium layer was deposited on the back surface. The structure is then annealed at 450 °C during 2h. It was found that Ln is increased, provided the initial value was smaller than 50 µm, and tht the mean density of dislocations is larger than 5 x 104 cm-2. Backside gettering appears to be the most likely mechanism to explain the results and it is assumed that dissolved oxygen may be involved.

Lateral reaction of polycrystalline silicon film with overlapping aluminum film

Remarkable substitution reaction between aluminum and polycrystalline silicon, which occurs below the eutectic temperature (577 °C), has been studied. This reaction proceeds laterally in the polycrystalline silicon film, and the reaction product contains aluminum. In order to elucidate the cause of the rapid reaction, the influences of aluminum volume, substrate materials, and polycrystalline silicon grain size on the reaction rate were investigated. Results indicate that the reaction proceeds preferentially along polycrystalline silicon grain boundaries on SiO2 substrate and depends on silicon solubility and diffusivity in aluminum.

MeV Helium Microbeam Analysis: Applications to Semiconductor Structures

ABSTRACTWe have employed an MeV He+ microbeam for the analysis of micron-scale semiconductor structures. The analysis combines a unique beam scanning and mapping capability with powerful ion beam techniques such as particleinduced x-ray emission, Rutherford backscattering and ion channeling. These analysis capabilities are applied to the measurement of dopant profiles in polycrystalline resistors, identification of micro-alloying in metal-GaAs contacts and damage/atom location in individual polycrystalline silicon grains. The latter application utilises the newly-developed technique of channeling contrast microscopy.

Deformation and recrystallization of polycrystalline silicon

A systematic study of recrystallization of hot-deformed single and polycrystalline silicon has been carried out. New grains were formed by nucleation and growth at temperatures between 1280 and 1410° C and the final grain size was a function only of the degree of deformation. For polycrystalline chemical vapour deposition (CVD)-grown silicon hot deformed at temperatures between 1 100 and 1310° C it was established that the largest grains (of the order of a few millimetres) can be grown after about 5% deformation. At this low strain the rates of nucleation and growth were low and consequently the time needed to complete recrystallization was rather long (20 h). Below 4% deformation no recrystallization occurred (critical degree of deformation is 4%). For both single and polycrystalline silicon grain growth after primary recrystallization was limited. This was due to the low mobility of high-angle grain boundaries in covalently bonded materials.

Grain growth of polycrystalline silicon films on SiO2 by cw scanning electron beam annealing

Reduced pressure, chemical vapor deposited polycrystalline silicon films (5000 Å thick) over thermally grown SiO2 on (100) silicon wafers are recrystallized by a scanning electron microscope modified electron beam annealing system. On the basis of transmission electron microscope bright-field images and electron diffraction patterns, large grained polycrystalline silicon films of 20-μm average grain size are obtained after electron beam annealing. Electron beam current, scanning rate, and annealing repetition are found to be important parameters in the recrystallization. Optimum values for them are from 1.6 to 1.9 mA, from 40 to 80 cm/sec, and from 5 to 10 times, respectively.

Arsenic Ion Channeling through Single Crystal Silicon

The main mechanism of anomalous tail generation in arsenic ion implanted layers is examined using silicon gate MOS capacitance flatband voltage and MOSFET threshold voltage measurements. Primarily, this approach measures the quantity of arsenic ions incorporated in silicon substrates as functions of polycrystalline silicon grain size. This method can measure ion amounts as low as 1011 cm−2 in the substrate. Only samples with large grains which extend across the polycrystalline silicon layer show flatband and threshold voltage shifts. Therefore, the mechanism of anomalous tail generation is attributed to arsenic ion channeling through single crystal silicon. Variations in the implant angle, as well as formation of a surface amorphous layer, are not sufficient to prevent channeling.

Laser Induced Controlled Nucleation and Growth Process For Large Grained Polycrystalline Silicon

ABSTRACTResearch on a new process is described which utilized a laser to achieve controlled crystallization of amorphous Si thinfilms for photovoltaic applications. Amorphous Si films are deposited on suitable substrates using RF sputtering. A laser is used to inoculate these films with crystalline embryos at specific locations. These embryos should then grow in a controlled atmosphere annealing furnace under conditions optimized to maintain the nucleation rate at zero and the transformation rate (from amorphous to crystalline silicon) at a maximum value. The result will be a polycrystalline silicon film with a large grain size to film thickness ratio, where the ultimate grain size will be determined by the laser inoculation spacing.

Enhanced crystallinity of silicon films deposited by CVD on liquid layers (CVDOLL process): Silicon on tin layers in the presence of hydrogen chloride

Chemical vapor deposition of silicon on a graphite substrate coated with a 5-μm-thick fluid tin layer provides a possibility for the production of large grained polycrystalline silicon layers. Using silane as a source material, crystallites can be produced with a mean grain size of about 20 μm, compared with 5 μm on a substrate without fluid layer. The grain size can be further enhanced by adding HCl as an etching agent to the gas phase. Mean crystallite sizes of 100 μm and larger can be obtained by the use of a fluid layer and a proper combination of SiH4 and HCl.