Graded Channel Research Articles

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Modeling of negative capacitance underlap graded-channel junction accumulation mode junctionless FET in nano-scale regime

Analytical modeling of negative capacitance (NC) graded-channel (GC) underlap junction accumulation mode (JAM) JL-FET is presented in this literature. Here, the surface potential, threshold voltage, sub-threshold drain current, sub-threshold swing (SS) and DIBL are obtained by solving the 2D Poisson's equation and Landau-Khalatnikov (LK) equation simultaneously. Performances of the proposed NC-GC-JAM-JL-FET is analyzed in detail for the variations in FE-layer thickness, gate-length, underlap length, graded channel ratio and Si-film thickness. The proposed model is calibrated with the experimental data to establish its acceptability. The proposed device is also simulated in the Silvaco ATLAS device simulator, which shows very good agreement with the analytical model. The present paper establishes the remarkable prospect of the proposed architecture to be operated for low-power application in nano-scale regime.

Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

Gate-all around (GAA) device is one of the cutting-edge technologies in the present semiconductor era owing to enhanced gate controllability and scalability at the nanoscale regime. The advantages of available GAA devices can further be improved by incorporating the dual material (DM) and graded channel (GC) techniques. To make use of these advantages, this manuscript investigates for the first time, the performance analysis of DMGC cylindrical GAA (DMGC CGAA) FET and its circuit applications such as inverter, NAND, NOR, ring oscillator and 6T static random-access memory (SRAM). Through the analysis, it has been found that the Ioff, SS, DIBL, and Ion/Ioff ratio are enhanced by an amount of 96.93%, 19.49%, 51.26%, and 96.98% respectively for DMGC CGAA FET when compared to single metal graded channel (SMGC) CGAA FET. Single-k (SiO2) and dual-k (SiO2+HfO2) techniques are also utilized here to analyse the device performance and dual-k recorded better performance in comparison with single-k owing to reduced off-state currents. It is noticed that delay has been reduced greatly for Inverter, NAND, and NOR by an amount of 51.93%, 11.25%, and 10.07% respectively for dual-k when compared to single-k DMGC CGAA FET. The frequency of oscillations for Ring Oscillator is improved by 69.7% with dual-k than single-k. Further, the obtained results of SRAM are compared with the existing literatures and noticed that the proposed DMGC CGAA FET outperforms the other works making the device a potential candidature for high performance applications.

Comparative of analog performance of transcapacitances in asymmetric self-cascode and graded-channel SOI nMOSFETs

This work presents a comparative study of the transcapacitances of an asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs with different gate lengths. This analysis was done by means of two-dimensional numerical simulations. Simulated results show the influence of others transcapacitances on the gate-to-gate capacitance for the ASC SOI device and the GC SOI device.

Compact analytical modeling of underlap gate stack graded channel junction accumulation mode junctionless FET in subthreshold regime

This paper presents the compact analytical model of underlap gate stack (GS) graded channel (GC) junction accumulation mode (JAM) junctionless (JL) FET. At first, a comparative analysis between the two different graded channel schemes and non-graded channel is performed based on ION, IOFF and ION/IOFF ratio. The scheme that yields the higher ION/IOFF ratio along with smaller IOFF, is adopted in the proposed JL FET for further analysis. The 2D analytical modeling of the GS-GC-JAM-JL FET deals with the determination of surface potential, threshold voltage, subthreshold drain current, DIBL and subthreshold swing. Results obtained from analytical model and simulations are compared and an excellent match is found. Thus the present paper establishes the outstanding ability of proposed underlap GS-GC-JAM-JL FET architecture to shield the short channel effects without sacrificing its performance, and therefore, proves it as a potential candidate for ultra-low power applications.

A design of nanoscale double-gate FET based ring oscillator with improved oscillation frequency using device engineering

In this paper, the performance of inverter and ring oscillator circuits based on the nanoscale double-gate (DG) FET is improved by using device engineering approaches. The modification of the parameters affecting the intrinsic delay time of the DGFET, such as on-current and the total gate capacitance can be improved the oscillation frequency of the ring oscillator. Accordingly, the effects of gate oxide thickness (tox) and body thickness (tbody) on the electrical characteristics of the device and circuit-level have been investigated so that we could provide a design of ring oscillator with improved oscillation frequency. Moreover, the enhanced source doping concentration and graded-channel (GC) techniques have been applied and analyzed at the device-level to ameliorate the oscillation frequency of the ring oscillator. Finally, we have presented the graded-channel (GC) strategy with two types of high-low (HL) and low-high (LH). The extracted results illustrate that the total gate capacitance of the LH-GC-DGFET is improved significantly compared to the HL-GC-DGFET. Consequently, the efficient design of the ring oscillator based on LH-GC-DGFET with superior oscillation frequency is proposed. The TCAD mixed-mode simulation has been used for simulating the circuits.

Analysis of Surface Potential and Electric Field for Fully Depleted Graded Channel Dual-Material-Double-Gate MOSFET through Modeling and Simulation

This article is about an elaborative description of two dimensional investigative mathematical structure of fully depleted graded channel (GC) dual-material-double-gate (DMDG) silicon-on-insulator metal–oxide–semiconductor-field-effect-transistor (SOI MOSFET). The surface potential contours in addition with electric field variation throughout the channel establish reduction of short-channel-effects (SCEs). To get better operational analysis, some new characteristics such as temperature effect and interface charge effects have been incorporated in the model. In this representation we also incorporate the consequences of high-k dielectric medium HfO2 instead of SiO2 and have made a comparison with the effect in various frameworks. In the GC DMDG composition, the surface potential as well as electric field throughout the channel shows close to step function variations which help to defeat the hot carrier along with drain-induced-barrier-lowering (DIBL) effects. As an outcome, the structure shows that the surface potential profile increases by using GC DMDG structure over DMDG. All these outcomes of the proposed analytical representation have been compared by TCAD simulation consequence. Very good conformity is observed between them.

Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors

The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.

Study of Matching Properties of Graded-Channel SOI MOSFETs

In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to validate the modelbased analysis both in linear and saturation regions.

Charge-Based Continuous Equations for the Transconductance and Output Conductance of Graded-Channel SOI MOSFET’s

This paper presents charge-based continuous equations for the transconductance and output conductance of submicrometer Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. The effects of carrier velocity saturation, channel length modulation and drain-induced barrier lowering were taken into account in the proposed equations. Experimental results were used to test the validity of the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement in a wide range of bias.

Study of the Drain Leakage Current Behavior in Graded-Channel SOI nMOSFETs Operating at High Temperatures

The theoretical and experimental study of drain leakage current behavior in Graded-Channel ( GC ) SOI nMOSFETs operating at high-temperatures ( up to 300oC ) is analyzed and discussed here. Through the studies it was noticed that drain leakage current depends strongly on the ratio between the length of the lowly doped region and the mask channel length. Also, it was observed that the drain leakage behavior is similar to the conventional SOI nMOSFETs which effective channel length being equal in both structures when the GC SOI nMOSFETs has the same channel doping level in the higher doped region. Numerical bidimensional simulations and experimental data were used in order to compare and discuss all the results.

2-D analytical modeling of drain and gate-leakage currents of cylindrical gate asymmetric halo doped dual material-junctionless accumulation mode MOSFET

This paper reports a physics-based analytical model for the cylindrical-gate (CG) asymmetric halo doped graded-channel (GC) dual-material (DM) junctionless-accumulation-mode (JAM) MOSFETs by incorporating both the effects of gate material engineering and channel engineering on the device characteristics. Poisson’s equation has been solved using the superposition technique with appropriate boundary conditions. The minimum central potential concept has been used to derive the threshold voltage model. The drain and gate currents have been modeled by including the effects of gate induced drain leakage (GIDL) and gate leakage currents, respectively. The performance parameters of the proposed CG-GCDM JAM MOSFETs have been compared with those of the CG-DM and CG-GC JAM-MOSFETs to show that the proposed structure has enhanced reliability against short channel effects (SCEs), hot carrier effects (HCEs) and various leakage currents (GIDL and gate leakage) for various control-to-screen gate length ratios. The proposed modeled results have been validated by comparing them with numerical data obtained by using a 3D commercial TCAD simulator.

Study on Impact of Parasitic Capacitance on Performance of Graded Channel Negative Capacitance SOI FET at High Temperature

This paper focuses on studying the impact of parasitic capacitance ( ${C}_{p}$ ) on the performance of nanoscale graded channel (GC) negative capacitance (NC) silicon-on-insulator (SOI) FET at elevated temperatures. The device performance has been extensively explored for a range of ${C}_{p}$ values for temperature range 300–400 K by employing simulation framework that uses TCAD models with Landau Khalatnikov equation. The advantages of GC design and NC phenomenon have been investigated for a wide temperature range and optimum values of ${C}_{p}$ have been obtained to achieve substantial enhancement in key device parameters such as differential voltage amplification, subthreshold swing (below 60 mV/dec), transconductance, transconductance efficiency, output characteristics, and unity gain frequency.

Analysis of Mismatching on the Analog Characteristics of GC SOI MOSFETs

This paper presents an evaluation of mismatching impact on the analog characteristics of fully-depleted graded-channel (GC) SOI MOSFET. This study is carried out by means of electrical measurements and two-dimensional numerical simulations, comparing GC to uniformly doped transistors. Important basic parameters such as threshold voltage and subthreshold slope were analyzed as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.

Surface Potential Modeling of Graded-Channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study

In each complementary metal-oxide-semiconductor (CMOS) technology generation, design of new device architectures at nanoscale regime becomes quite challenging task due to increased short channel effects (SCEs) and leakage current. A double-gate (DG) MOSFET is an alternative structure. To enhance the performance of DG MOSFET, gate stack (GS) and dual-material gate (DMG) with graded-channel (GC) concepts are amalgamated. Analytical surface potential modeling of GCGS DMDG MOSFET has been done by solving the two-dimensional (2D) Poisson’s equation with suitable boundary conditions. The surface potential profile of GCGS DMDG MOSFET shows a step variation at the interface of two materials. The electrical parameters drain induced barrier lowering (DIBL), sub-threshold swing (SS) and on-current to off-current $\left (\frac {I_{on}}{I_{off}}\right )$ ratio reveals that, DMDG shows a better performance over single-material (SM) DG MOSFET with all (Si3N4, HfO2 and Ta2O5) GS high-k dielectric configurations. An enhanced performance in GCGS DMDG is due to the fact of increased average carrier velocity, reduced drain field effect and leakage current. Further, analog/RF performance parameters such as transconductance (gm), transconductance generation factor (TGF), cut-off frequency (fT), transconductance generation frequency product (TGFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are extracted and compared for both SMDG and DMDG MOSFET with HfO2 GS configuration. The efficacy of analytically modeled results is compared with numerically simulated results obtained from 2D ATLAS device simulator.

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.

A Charge-Plasma-Based Transistor With Induced Graded Channel for Enhanced Analog Performance

In this paper, using the charge-plasma concept, we propose an effective technique to implement a graded channel (GC) nanoscale MOSFET without the need for a separate implantation. The characteristics are demonstrated and compared with conventional dopingless, junctionless, and underlap inversion-mode MOSFET. The results show that the proposed GC device exhibits reduced drain-induced barrier lowering, improved intrinsic gain ( ${A} _{V}$ ), cutoff frequency ( ${f} _{T}$ ), and maximum oscillation frequency ( ${f} _{\mathrm{MAX}}$ ). Our approach overcomes the difficulty of creating a narrow GC doping profile and, thus, makes the GC MOSFET more attractive in carrying on with the scaling trend. The possible fabrication process flow of GC-double-gate (DG) FET is also proposed.

Some Device Design Considerations to Enhance the Performance of DG-MOSFETs

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current (<TEX>$I_{off}$</TEX>), on current (<TEX>$I_{on}$</TEX>), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

Analog Behavior of Submicron Graded-Channel SOI MOSFETs Varying Channel Length, Doping Concentration and Temperature

In this paper the analog performance of Graded-Channel (GC) SOI nMOSFETs with deep submicrometer channel length is presented. Experimental data of GC transistors fabricated in an industrial 150 nm fully-depleted SOI technology from OKI Semiconductorswere used to adjust the two-dimensional numerical simulations, in order to analyze the devices analog behavior by extrapolating their physical parameters. The obtained results show that the larger intrinsic voltage gain improvement occurs when the length of the lightly doped region is approximately 100 nm regardless the total channel length, doping concentration and temperature.

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs

In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150K) is presented. This analysis has been carried out through experimental measurements of Common-source, Cascode and Wilson current mirrors architectures. The advantages of the use of graded-channel transistors for implementation of current mirrors in comparison to standard ones is discussed, focusing on the increase of output swing and output resistance. In all architectures some performance degradation has been observed with the temperature reduction, although current mirrors with GC transistors still present better performance than those implemented with standard SOI transistors. Two-dimensional numerical simulations were performed in order to further investigate the behavior of graded-channel current mirrors, looking at the bias condition of each transistor in the current mirror architectures. The obtained results indicate that good performance, compared to that of GC current mirrors, may be obtained by combining both standard and graded-channel transistors, rather than using the same channel engineering for all devices in the circuit.