A design of nanoscale double-gate FET based ring oscillator with improved oscillation frequency using device engineering

Abstract

In this paper, the performance of inverter and ring oscillator circuits based on the nanoscale double-gate (DG) FET is improved by using device engineering approaches. The modification of the parameters affecting the intrinsic delay time of the DGFET, such as on-current and the total gate capacitance can be improved the oscillation frequency of the ring oscillator. Accordingly, the effects of gate oxide thickness (tox) and body thickness (tbody) on the electrical characteristics of the device and circuit-level have been investigated so that we could provide a design of ring oscillator with improved oscillation frequency. Moreover, the enhanced source doping concentration and graded-channel (GC) techniques have been applied and analyzed at the device-level to ameliorate the oscillation frequency of the ring oscillator. Finally, we have presented the graded-channel (GC) strategy with two types of high-low (HL) and low-high (LH). The extracted results illustrate that the total gate capacitance of the LH-GC-DGFET is improved significantly compared to the HL-GC-DGFET. Consequently, the efficient design of the ring oscillator based on LH-GC-DGFET with superior oscillation frequency is proposed. The TCAD mixed-mode simulation has been used for simulating the circuits.