Graded Channel Research Articles

TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET

In this paper, the effect of various device design engineerings such as channel engineering, i.e., graded channel (GC), gate stack (GS) engineering (high-κ), and dual-material gate (DMG) on double-gate MOSFET (DG MOSFET) have been analyzed using ATLAS device simulator. Furthermore, the combinations of these technologies i.e., GC, along with GS engineering, i.e., GCGSDG, and GS together with DMG, i.e., GS dual-material DG (GSDMDG), have been taken into consideration. The simulation results demonstrate that, out of the several design engineerings, the GCGSDG is the most suitable for high-speed switching applications. However, the GSDMDG provides superior performance as an amplifier.

Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-Off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain (AVO_OTA) along with three times higher cutoff frequency (fT_OTA) as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle (s/ σ) ratio of 3.2 and operated below a bias current (IBIAS) of 80 μA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology.

Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors

The development of models to simulate circuits containing new devices is an important task to allow for the introduction of these devices in practical applications. In this paper we show the advantages of using the Symmetric Doped Double-Gate Model recently developed and are already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. A current-mirror circuit using GC devices has been simulated and the results were validated comparing them with those obtained in MIXED-MODE and two-dimensional ATLAS simulation of the GC devices.

Performance of Common-Source, Cascode and Wilson Current Mirrors Implemented with Graded-Channel SOI nMOSFETs in a Wide Temperature Range

This work presents an experimental comparative analysis of the behavior of current mirrors implemented with standard uniformly doped and Graded-Channel (GC) SOI nMOSFETs as a function of the temperature. Three different current mirror architectures were used, Common-source, Wilson and Cascode. The experimental results show that the use of Graded-Channel transistors promotes not only the increase of the output swing, but also the increase of the output resistance in all evaluated architectures, in comparison to the standard uniformly doped counterpart. Despite some degradation observed with the temperature reduction, current mirrors with GC transistors still present better performance than those implemented with standard SOI transistors.

Analytical Modeling of Double Gate Graded-Channel SOI Transistors for Analog Applications

In this work we present the development of an analytical model for double gate (DG) Silicon-on-Insulator (SOI) nMOSFET transistor with graded-channel (GC), valid from weak inversion to strong inversion. Atlas numerical two-dimensional simulations and experimental results are used to validate the proposed model. Good agreement between simulated, modeled and experimental results is demonstrated.

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software.

Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SOI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures.

Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

In this work the performance of graded-channel (GC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with GC and standard SOI MOS devices considering the same mask dimensions. It is shown that by using GC devices, buffer gain very close to the theoretical limit can be achieved, with improved linearity, while for standard devices the gain departs from the theoretical value depending on the inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to confirm some hypotheses proposed to explain the gain behavior observed in the experimental data. By using numerical simulations the channel length has been varied, showing that the gain of buffers implemented with GC devices remains close to the theoretical limit even when short-channel devices are adopted. It has also been shown that the length of a source-follower buffer using GC devices can be reduced by a factor of 5, in comparison with a standard SOI MOSFET, without gain loss or linearity degradation.

A Series Association Model For Double Gate Graded-Channel SOI nMOSFET Analog Circuit Simulation

In this work we present the development of an equivalent series association analytical model for double gate (DG) Silicon-on-Insulator (SOI) nMOSFET transistor with graded-channel (GC) that is valid from weak inversion to strong inversion. Through the use of DG analytical models available in the literature, considering an equivalent structure represented by two transistors with different doping levels in series association, with short-circuited gates, each one simulating a GC channel region, we have got a model of the DG GC SOI nMOSFET. Atlas numerical two-dimensional simulations and experimental results are used to validate the proposed model. Good agreement between simulated, modelled and experimental results is found.

Channel Length Influence on the Performance of Source-Follower Buffers Implemented with Graded-Channel SOI nMOSFETs

This work presents an evaluation of the influence of channel length on the performance of graded-channel (GC) SOI nMOSFETs operating as source-follower buffers. Experimental data is used to compare the buffer gain and linearity of GC and standard SOI nMOS transistors for different mask channel lengths and similar effective channel length. Two-dimensional numerical simulations were also performed, showing that the gain of buffers implemented with GC devices remains close to the theoretical limit even when short-channel devices are used. The simulated results indicate that the length of a source-follower buffer using GC devices can be reduced by a factor of 5, in comparison with the standard counterpart, without gain degradation or linearity worsening.

Linearity Analysis in Double Gate Graded-Channel Soi Devices Applied to 2-Mos Mosfet-C Balanced Structures

This paper examines the linearity of 2-MOS MOSFET-C balanced structures using conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices. The distortion analysis has been performed through the evaluation of third order harmonic distortion (HD3). The study has been carried out through experimental results, two-dimensional process and device simulations. Along this work, the best operation bias in terms of HD3 is determined for each analysed device and the couple device that exhibits lower HD3 is pointed out. The use of GC GAA devices in 2-MOS structures has showed to improve the linearity in relation to the conventional GAA. Finally, a discussion over the non-linearities causes is performed clarifying their origins and the improvement provided by the adoption of GC GAA devices in 2-MOS structures.

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15dB improved linearity. The influence of channel length reduction on the HD is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level.

Channel Length Reduction Influence on Harmonic Distortion of Graded-Channel Gate-All-Around Devices

This work compares the linearity of conventional and Graded- Channel (GC) Gate-All-Around (GAA) devices for analog operation as in an amplifier when the channel length is scaled. The study has been performed through two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar bias the performance of GC GAA transistors remains better than the uniformly doped GAA for any channel length. Although scaling the devices tends to degrade the harmonic distortion, significant results were obtained for the GC configuration measured as an improvement of more than 15 dB in total harmonic distortion-to-gain ratio operating in the same region with channel length of 1μm and with lightly doped region length of 0.3 μm.

Analysis of Self-Heating Effect in Graded-Channel Silicon-on-Insulator nMOSFETs

This paper presents a Self-Heating (SH) analysis using conventional Silicon-On-Insulator (SOI) in comparison to Graded- Channel (GC) SOI nMOSFETs devices. The analysis is performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations are performed in both studies considering the lattice heating. The models and the thermal conductive constant used in these simulations are also presented. It is demonstrated that GC devices with the same mask channel length presents similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel length, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference.

Charge-Based Continuous Explicit Equations for the Transconductance and Output Conductance of Submicron Graded-Channel SOI MOSFET'S

This paper presents charge-based continuous explicit equations for the transconductance and output conductance of submicron Graded- Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. Short-channel effects like channel length modulation, velocity saturation and drain- induced barrier lowering have been considered in the proposed expressions. Experimental results were used to test the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement as well as smooth transitions between the different regions of operation, validating the proposed equations.

Analysis of Silicon Thickness Reduction on Analog Parameters of GC GAA SOI Transitors Operating up to 300{degree sign}C

This paper analyzes the impact of silicon film thickness reduction in some analog parameters of Gate-All-Around (GAA) transistors using the graded-channel (GC) architecture. The study was done at high temperatures (up to 300{degree sign}C) through two- dimensional simulations. As the silicon film is reduced an improvement on the Early voltage was observed. However, for GC GAA devices this improvement is more pronounced at room temperature than at high temperatures. The output swing voltage (VOS) was also studied and it decreases while reducing the silicon thickness. Regarding the GC GAA the VOS is larger than conventional GAA in 50 nm thick transistors.

Impact of Graded-Channel SOI MOSFET Application on the Performance of Cascode and Wilson Current Mirrors

This work shows the impact of the use of graded-channel SOI MOSFETs (GC) in Wilson and Cascode current mirrors. The study was made through bi-dimensional simulations and experimental measurements, focusing on the mirroring precision, the output swing voltage (VOS) and output resistance of each architecture comparing with the conventional SOI devices. It was observed that the devices of graded-channel (GC) presented some improvement in the mirroring precision and a significant increase in the output resistance and output swing in all the architectures studied if compared to standard fully depleted SOI MOSFET. the setting time of GC current mirrors has been Also studied and has demonstrated improvements in relation to conventional SOI devices.

Analysis of Matching in Graded-Channel SOI MOSFETs

This paper presents an analysis of mismatch in Graded-Channel (GC) SOI MOSFETs. Experimental results show that GC devices present poorer threshold voltage and drain current matching in comparison to conventional SOI counterpart. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to predict the matching behavior both in linear and saturation regions.

Application of Double Gate Graded-Channel SOI in MOSFET-C Balanced Structures

This work studies the linearity of conventional and Graded- Channel (GC) Gate-All-Around (GAA) devices when applied in 2- MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive.

Impact of graded channel (GC) design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short channel immunity and hot carrier reliability

In the present paper, a two-dimensional (2-D) analytical model for graded channel fully depleted cylindrical/surrounding gate MOSFET (GC FD CGT/SGT) has been developed by solving the Poisson’s equation in cylindrical coordinates. An abrupt transition of silicon film doping at the interface has been assumed and the effects of the doping and the lengths of the high and low doped regions have been taken into account. The model is used to obtain the expressions of surface potential and electric field in the two regions. The analysis is extended to obtain the expressions for threshold voltage ( V th) and subthreshold swing. It is shown that a graded doping profile in the channel leads to suppression of short channel effects (SCEs) like threshold voltage roll-off, drain induced barrier lowering (DIBL) and hot carrier effects. The results so obtained have been compared with simulated results obtained using the device simulator ATLAS 3D and are found to be in good agreement.