Good Data Retention Research Articles

Record Resistance Ratio and Bipolar/Unipolar Resistive Switching Characteristics of Memory Device Using Germanium Oxide Solid Electrolyte

The bipolar and unipolar resistive switching characteristics of a memory device using a Cu filament in a new Cu/GeOx/W structure under low-voltage operation (<1.5 V) have been investigated. The germanium oxide (GeOx) solid electrolyte with a thickness of approximately 12 nm has been observed by both high-resolution transmission electron microscopy (HRTEM) and energy-dispersive X-ray spectroscopy analyses. A small device size of 150×150 nm2 has been observed by HRTEM. The composition of Ge:O has been investigated by X-ray photoelectron spectroscopy analysis. The memory device shows bipolar switching under current compliances of 1 nA–50 µA with a large SET voltage of approximately 0.5 V and unipolar switching with a larger current compliance of >100 µA. This memory device has excellent uniformity in SET/RESET voltages, low resistance state/high resistance state (LRS/HRS), long read endurance of >1×105 cycles, and good data retention of >1×104 s with high resistance ratios of >105 in the bipolar mode and >109 in the unipolar mode.

Characterization of In20Ge15Sb10Te55Phase Change Material for Phase Change Memory with Low Power Operation and Good Data Retention

Characterization of In₂₀Ge₁₅Sb₁₀Te₅₅Phase Change Material for Phase Change Memory with Low Power Operation and Good Data Retention

Characterization of In20Ge15Sb10Te55 Phase Change Material for Phase Change Memory with Low Power Operation and Good Data Retention

An indium-incorporated germanium–antimony–telluride material, In20Ge15Sb10Te55 (IGST), was investigated as a recording material for phase change memory. The crystallization temperature of IGST was 226 °C, which is 75 °C higher than that of conventional GST. The reset current of the device using IGST was about 10 mA for a plug 180 nm in diameter, which enabled a low-power operation, compared with the GST-based device. A cycle endurance of up to 1.5×104 was achieved. The data retention was estimated to be 10 years at 145 °C. These data clearly show that IGST exhibits promising characteristics as a recording material for phase change memory.

High-Speed Multilevel nand Flash Memory With Tight $V_{\rm th}$ Distribution Using an Engineered Potential Well and Forward-Bias Adjusted Programming

This paper reports a high-speed multilevel-cell nand Flash memory device using a Si- SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -TiN- TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -TaN (SOTTOT) engineered potential well (EW). The SOTTOT EW Flash memory device has very fast cell programming speed and good data retention. A 16-kbit nand memory block using SOTTOT cells was programmed using a forward-bias-adjusted programming scheme, which enables bit adjustability during page programming to suppress the development of fast bits. The SOTTOT memory block shows fast programming speed (~40 μs/page), tight threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) distribution (~0.22 V/level), and clear <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> -level margins (~0.9 V) for the eight-level programming. The SOTTOT memory block also shows good resistance against pass/read disturbances as well as good ten-year data retention at an ambient temperature of 75 °C throughout 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> programming/erasing cycling.

Improved charge trapping flash device with Al2O3/HfSiO stack as blocking layer

In this paper, we investigate an Al2O3/HfSiO stack as the blocking layer of a metal—oxide—nitride—oxide—silicon-type (MONOS) memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the blocking layer or an Al2O3/HfO2 stack as the blocking layer, the sample with the Al2O3/HfSiO stack as the blocking layer shows high program/erase (P/E) speed and good data retention characteristics. These improved performances can be explained by energy band engineering. The experimental results demonstrate that the memory device with an Al2O3/HfSiO stack as the blocking layer has great potential for further high-performance nonvolatile memory applications.

Device Characteristics of a Ge-doped SbTe alloy for High-speed Phase-change Random Access Memory

We investigated the influence of phase-change materials on the device performance for low-power and high-speed phase-change random access memory (PCRAM). The Ge-doped SbTe (Ge-ST) alloy was used as a phase-change material and was compared with the conventional Ge2Sb2Te5 (GST225) alloy. An as-deposited Ge-ST film grown by using chemical vapor deposition had an amorphous phase which showed the superior gap-fill capability compared to as-deposited crystalline GST225. The crystallization time for the set operation was decreased to 80 ns, and the reset current reduced to 0.16 mA when Ge-ST was introduced in sub-40 nm a PCRAM. In addition, the Ge-ST alloy showed a good data retention property of 10 years guaranteed at 100 ◦C. These results will enable us to realize low-power and high-speed PCRAM devices beyond the sub-40 nm design rule.

Carbon-doped GeTe: A promising material for Phase-Change Memories

This paper investigates Carbon-doped GeTe (GeTeC) as novel material for Phase-Change Memories (PCM). In the first part of the manuscript, a study of GeTeC blanket layers is presented. Focus is on GeTeC amorphous phase stability, which has been studied by means of optical reflectivity and electrical resistivity measurements, and on GeTeC structure and composition, analyzed by XRD and Raman spectroscopy. Then, electrical characterization of GeTeC-based PCM devices is reported: resistance drift, data retention performances, RESET current and power, and SET time have been investigated. Very good data retention properties and reduction of RESET current make GeTeC suitable for both embedded and stand-alone PCM applications, thus suggesting GeTeC as promising candidate to address some of the major issues of today’s PCM technology.

Effect of Program/Erase Speed on Switching Uniformity in Filament-Type RRAM

We investigated the effect of program/erase speed on switching uniformity in filament-type resistive memory with Mo/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Pt structure. The RRAM device exhibits a large on/off ratio (>; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ), good data retention properties even at 200°C, and stable pulse-switching endurance up to 106 cycles. In comparison with slow switching operation, fast switching operation achieves more uniform program/erase performance in filament-type resistive memory. In order to determine the relationship between the switching speed and the uniformity, we carried out an effective analysis of real pulse operation.

A Novel Ni/WOX/W Resistive Random Access Memory with Excellent Retention and Low Switching Current

The behavior of WOX resistive random access memory (ReRAM) is a strong function of the top electrode material, which controls the conduction mechanism and the forming process. When using a top electrode with low work function, the current conduction is limited by space charges. On the other hand, the mechanism becomes thermionic emission for devices with a high work function top electrode. These (thermionic) devices are also found to have higher initial resistance, reduced forming current, and larger resistance window. Based on these insights and considering the compatibility to complementary metal–oxide–semiconductor (CMOS) process, we proposed to use Ni as the top electrode for high performance WOX ReRAM devices. The new Ni/WOX/W device can be switched at a low current density less than 8×105 A/cm2, with RESET/SET resistance ratio greater than 100, and extremely good data retention of more than 300 years at 85 °C.

Investigation of resistive switching behaviours in WO3-based RRAM devices

In this paper, a WO3-based resistive random access memory device composed of a thin film of WO3 sandwiched between a copper top and a platinum bottom electrodes is fabricated by electron beam evaporation at room temperature. The reproducible resistive switching, low power consumption, multilevel storage possibility, and good data retention characteristics demonstrate that the Cu/WO3/Pt memory device is very promising for future nonvolatile memory applications. The formation and rupture of localised conductive filaments is suggested to be responsible for the observed resistive switching behaviours.

Improved Bipolar Resistive Switching Memory Using W/TaO&lt;sub&gt;x&lt;/sub&gt;/W Structure

Resistive switching memory characteristics of high- TaOx film in a W/TaOx/W structure have been investigated and compared with Al/TaOx/W structure. Amorphous TaOx film with a thickness of 6.8 nm was confirmed by HRTEM image and EDX analysis. The switching in Al/TaOx/W structure is found to be unstable with large variations in set and reset voltages. The memory device in W/TaOx/W structure shows good memory characteristics with a low power of ~500µAx1.6V. The current conduction mechanism is fitted to Ohmic and SCLC in LRS and HRS, respectively. The memory device has shown good endurance characteristics of &gt;5x103 cycles and good data retention with a stable HRS/LRS.

Low-Consumption Phase Change Material with Good Data Retention Selected from Sb&lt;SUB&gt;x&lt;/SUB&gt;Te

Various compositions of SbxTe phase-change films have been investigated by means of in situ temperature-dependent resistance measurement. Although crystallization temperature of Sb3Te is about 536 K, a little lower than those of Sb2Te and Sb4Te, it has a better data retention performance than the other two compositions. X-ray diffraction patterns imply that poly-crystalline structures of Sb-Te alloys are all hexagonal, and phase separation appears in SbTe3, Sb2Te, Sb3Te and Sb4Te alloys. Sb2Te and Sb3Te have been selected for phase-change random access memory devices. RESET voltage for Sb3Te is 1.2 V when the voltage pulse width is 50 ns, 0.3 V lower than that for Sb2Te. By using the voltage pulse width of 200 ns, Sb3Te needs 1.8 V and 4 V to complete SET-RESET performance, 0.4 V and 0.5 V lower than Sb2Te respectively. It indicates that Sb3Te is more suitable for the application of phase-change random access memory.

A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals

In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.

Effect of ZrOx/HfOx bilayer structure on switching uniformity and reliability in nonvolatile memory applications

We have investigated the bilayer structure of binary oxides such as HfOx and ZrOx for applications to resistance memory. The ZrOx/HfOx bilayer structure shows a lower reset current and operating voltage than an HfOx monolayer under dc sweep voltage. Furthermore, the bilayer structure exhibits a tight distribution of switching parameters, good switching endurance up to 105 cycles, and good data retention at 85 °C. The resistive switching mechanism of memory devices incorporating the ZrOx/HfOx bilayer structure can be attributed to the control of multiple conducting filaments through the occurrence of redox reactions at the tip of the localized filament.

Nanofloating Gate Memory Devices Based on Controlled Metallic Nanoparticle-Embedded InGaZnO TFTs

In this letter, InGaZnO thin-film transistor (bottom-gate (n <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$+$</tex> </formula> Si) and top-contact structure)-based nanofloating gate memory devices were developed. These nonvolatile transistor memory devices contained self-assembled gold nanoparticles ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$ \hbox{Au}_{\rm NP}$</tex></formula> ) and exhibited good programmable memory characteristics according to the programming/erasing operations with large memory windows. The charge trapping in the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\hbox{Au}_{\rm NP}$</tex></formula> charge storage layers was responsible for the memory operations. The good endurance and data retention capability demonstrated by these memory devices make them suitable for nonvolatile memory applications. As this approach was based on the solution-processed controlled <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\hbox{Au}_{\rm NP}$</tex></formula> charge trapping layers and the low-temperature synthesized transparent oxide semiconductors, it has the potential for application in low-temperature-processed transparent nonvolatile memory devices.

High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in nor-Type Flash Memory

For the first time, a high-performance (τPGM = 200 ns/τERS = 5 ms) cell with superior reliability characteristics is demonstrated in a nor-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate silicon-oxide-nitride-oxide-silicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight VTH distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.

P-Channel Nonvolatile Flash Memory With a Dopant-Segregated Schottky-Barrier Source/Drain

A p-channel dopant-segregated-Schottky-barrier (DSSB) device based on a SOI FinFET structure is proposed for silicon-oxide-nitride-oxide-silicon type Flash memory, providing the feasibility of bit-by-bit operation through the aid of a symmetric program/erase operation. This concept is based on utilizing injected holes due to enhanced Fowler–Nordheim tunneling probability triggered by the sharpened energy band bending at the DSSB source/drain junctions as a programming method and the tunneled electrons from a silicon channel as an erasing method. As a result, a threshold voltage window of nearly 4 V and good data retention are achieved within a P/E time of 3.2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{s}$</tex></formula> .

Electrode dependence of resistive switching in Mn-doped ZnO: Filamentary versus interfacial mechanisms

We carry out a comparative study on resistive switching in Mn-doped ZnO thin films; samples grown on Pt and Si show unipolar and bipolar switching behaviors, respectively. Fittings of the current-voltage curves and area dependence of the device resistance reveal the filamentary conduction in Pt/Mn:ZnO/Pt. On the other hand, the interfacial effect dominates in Pt/Mn:ZnO/Si, and its low resistance state exponentially relaxes toward the high resistance state in contrast to the good data retention in Pt/Mn:ZnO/Pt. Our results suggest that selecting electrodes dictates the resistive switching mechanism presumably by affecting the migration dynamics of oxygen vacancies.

Organic Field-Effect Transistor-Based Nonvolatile Memory Devices Having Controlled Metallic Nanoparticle/Polymer Composite Layers

Nonvolatile memory devices based on the pentacene film and controlled gold nanoparticle (Au np )/polymer composite layers were developed. Organic field-effect transistor-based nonvolatile memory devices having self-assembled Au np exhibited controllable and reliable current level differences (on- and off-states) according to the applied gate voltages (programming/erasing operations). The memory devices showed large memory windows as well as good data retention properties by adopting charge storage layers of controlled Au np separated by insulating polymer layers. The process for fabricating nonvolatile memory devices was based on the solution processes and organic semiconductor layers, so it has a potential use in flexible nonvolatile memory applications.

Enhance the split-gate flash cell performance by partially decoupling the SG oxide thickness from the tunnel oxide thickness

In this paper, a method is proposed to enhance the self-aligned split-gate flash cell performance. Utilizing the different oxidation rate between silicon substrate and the heavily-doped poly-silicon sidewall of the floating gate, a rapid-thermal-oxidation step before oxide deposition is proved to be effective to decouple the tunnel oxide thickness from the select gate (SG) oxide thickness. 0.18 μm self-aligned split-gate flash cell fabricated with this method is characterized. The erase speed is shown slightly faster even with the erase voltage lowered by 1 V. The read current in erased state is improved by 70%. Good endurance and data retention performances are also demonstrated.