Global Process Variations Research Articles

A Fully Differential Analog Front-End for Signal Processing from EMG Sensor in 28 nm FDSOI Technology

This paper presents a novel analog front-end for EMG sensor signal processing powered by 1 V. Such a low supply voltage requires specific design steps enabled using the 28 nm fully depleted silicon on insulator (FDSOI) technology from STMicroelectronics. An active ground circuit is implemented to keep the input common-mode voltage close to the analog ground and to minimize external interference. The amplifier circuit comprises an input instrumentation amplifier (INA) and a programmable-gain amplifier (PGA). Both are implemented in a fully differential topology. The actual performance of the circuit is analyzed using the corner and Monte Carlo analyses that comprise fifth-hundred samples for the global and local process variations. The proposed circuit achieves a high common-mode rejection ratio (CMRR) of 105.5 dB and a high input impedance of 11 GΩ with a chip area of 0.09 mm2.

A MEMS-Based Optical Scanning System for Precise, High-Speed Neural Interfacing

Optical scanning is a prevalent technique for optical neural interfaces where light delivery with high spatial and temporal precisions is desired. However, due to the sequential nature of point-scanning techniques, the settling time of optical modulators is a major bottleneck for throughput and limits random access targeting capabilities. While fast lateral scanners exist, commercially available varifocal elements are constrained to 3-ms settling times, limiting the speed of the overall system to hundreds of hertz. Faster focusing methods exist but cannot combine fast operation and dwelling capability with electrical and optical efficiency. Here, we present a varifocal mirror comprised of an array of piston-motion micro-electromechanical systems (MEMS) micromirrors and a custom driver application specific integrated circuit (ASIC), offering fast operation with dwelling capability while maintaining high diffraction efficiency. The ASIC features a reconfigurable nonlinear digital-to-analog converter (DAC) to simultaneously compensate for the built-in nonlinearity of electrostatic actuators and the global process variations in MEMS mirrors. Experimental results demonstrate a wide continuous sweeping range that spans 22 distinctly resolvable depth planes with refresh rates greater than 12 kHz.

STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

This paper presents a novel architecture for in-memory computation of binary neural network (BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are fed through bitlines, then, a BNN vector multiplication can be done by single sensing of the merged SL voltage of a row. Our design allows to perform unrestricted accumulation across rows for full utilization of the array and BNN model scalability, and overcomes challenges on the sensing circuit due to the limitation of low regular tunneling magnetoresistance ratio (TMR) in STT-MRAM. Circuit techniques are introduced in the periphery to make the energy-speed-area-robustness tradeoff more favorable. In particular, time-based sensing (TBS) and boosting are introduced to enhance the accuracy of the BNN computations. System simulations show 80.01% (98.42%) accuracy under the CIFAR-10 (MNIST) dataset under the effect of local and global process variations, corresponding to an 8.59% (0.38%) accuracy loss compared to the original BNN software implementation, while achieving an energy efficiency of 311 TOPS/W.

On-chip static and dynamic monitors for low power applications

Due to the increasing demand for battery-operated mobile devices in the market, low power consumption inside the chip is an essential ingredient during the chip design. Static and dynamic monitors are needed to achieve low power in modern chips. The static or process monitor provides information about global and local process variation inside the chip. The dynamic or in situ monitor provides information about the global, local, and environmental variation on the critical path of the design inside the chip. In this work, a static monitor is discussed using a reconfigurable ring oscillator which extracts the threshold voltage information. A dynamic monitor using warning flip-flop is discussed which can be used for dynamic voltage and frequency scaling to achieve low power consumption. Both static and dynamic monitors are experimentally validated in a test chip, that is implemented in CMOS 130 nm technology node.

An Active Resistor With a Lower Sensitivity to Process Variations, and its Application in Current Reference

A novel active resistor circuit offering less sensitivity to process and temperature variations without any extra trimming is proposed. The circuit consists of two accurately matched, high resistance polysilicon (hripoly) resistors and a voltage-controlled MOS resistor, and it is designed for the industrial temperature range (-20 °C to 85 °C) in the TSMC 180 nm general-purpose process. The actual performance of the circuit is analyzed by using the Corner and Monte Carlo analyses that comprise two thousand samples for the global and local process variations. The maximum error in the resistor value is ±6.2 %, with the standard deviation of σ = 1.2 %. The proposed active resistor reduces the maximum error from ±15 % to ±6.2 % when the both the process and the temperature variations are considered without trimming. As an application, a transconductor and a current reference based on the novel active resistor are introduced, and their accuracy-related performance is studied.

Ultra‐low‐voltage GDI‐based hybrid full adder design for area and energy‐efficient computing systems

In recent years, ultra-low-voltage (ULV) operation is gaining more importance for achieving minimum energy consumption. Full adder is the basic computational arithmetic block in many of the computing and signal/image processing applications. Here, a new hybrid 1-bit full adder circuit which employs both Gate Diffusion Input (GDI) logic and multi-threshold voltage (MVT) transistor logic is reported. The main objective of the proposed MVT-GDI-based hybrid full adder design is to provide minimum energy consumption with less area. The proposed hybrid design is simulated using standard 45 nm CMOS process technology at an ULV of 0.2 V. The post-layout simulation results have shown that the proposed design achieved significant improvements in comparison with the other reported designs by achieving >57%, 92% savings in the Energy and EDP, respectively, with only 14 transistors. Monte–Carlo simulations have also been performed and is found that the proposed design methodology yields full functionality and robustness against local and global process variations. Normalised energy metrics to 32 and 22 nm technologies shows that the proposed design achieves >57% energy savings in prior to the recent works.

A Process-Independent and Highly Linear DCO for Crowded Heterogeneous IoT Devices in 65-nm CMOS

The Internet of Things (IoT) devices are manufactured under different fabrication quality standards, considering the wide variety of vendors. As a result, global process variations in the IoT system-on-chip (SoC) are an enormous concern that can affect reliability of the device. Among the components in a typical SoC, oscillator is the most susceptible element to process variations. This paper proposes a feedback-assisted digitally controlled oscillator (DCO). The DCO has 512 operating modes, for wide-range frequency tuning from 0.6 to 3.1 GHz. By adding a dynamic feedback to inner current-controlled oscillator using a frequency-to-current converter, the DCO remains linear and invariant to the process for entire 2.5-GHz frequency band. Thanks to pseudodifferential cross-coupled structure used in each stage, this paper achieves a 2.3 ps deterministic jitter at 1.87-GHz output frequency. Furthermore, Monte Carlo analysis is performed at 1.87-GHz frequency; indicate that standard deviation from the mean is 2.47% that verifies reliability of this design. Power consumption varies from 0.86 to 3.68 mW at 1.2 V supply voltage, corresponding to the code word. The DCO is implemented in 65-nm standard CMOS process.

Fully integrated high quality factor <i>G</i><sub>m</sub><i>C</i> bandpass filter stage with highly linear operational transconductance amplifier

Abstract. This paper presents an electrical, fully integrated, high quality (Q) factor GmC bandpass filter (BPF) stage for a wireless 27 MHz direct conversion receiver for a bendable sensor system-in-foil (Briem et al., 2016). The core of the BPF with a Q factor of more than 200 is an operational transconductance amplifier (OTA) with a high linearity at an input range of up to 300 mVpp, diff. The OTA's signal-to-noise-and-distortion-ratio (SNDR) of more than 80 dB in the mentioned range is achieved by stabilizing its transconductance Gm with a respective feedback loop and a source degeneration resistors RDG. The filter stage can be tuned and is tolerant to global and local process variations due to offset and common-mode feedback (CMFB) control circuits. The results are determined by periodic steady state (PSS) simulations at more than 200 global and local process variation parameter and temperature points and corner simulations. It is expected, that the parasitic elements of the layout have no significant influence on the filter behaviour. The current consumption of the whole filter stage is less than 600 µA.

Optimal transistor sizing for maximum yield in variation‐aware standard cell design

SummaryProcess variability, in addition to wide temperature and supply voltage variation ranges, severely degrades the fabrication outcome (yield) of digital cells as for the fulfillment of performance specification bounds. This paper presents the application of mathematical optimization to the design of standard cells that are robust to process variations even in worst‐case operating conditions. The method attains the optimal sizing of individual transistors in the cell for maximizing the statistical yield referring to leakage power and propagation delay bounds, with local and global process variations specified by industrial process development kits (PDKs). The approach is demonstrated for a 40 nm low‐power standard threshold voltage Complementary Metal Oxide Semiconductor (CMOS) technology, for an intended operating temperature range [−40 °C, 125 °C] and supply voltage range [0.95 V, 1.05 V]. The reported optimization results show a yield improvement from an initial 50% to 99.9%, and Simulation Program with Integrated Circuit Emphasis (SPICE)‐level Monte Carlo analysis confirmed the estimated yield of the obtained circuits. Copyright © 2015 John Wiley & Sons, Ltd.

Full-Swing Gate Diffusion Input logic—Case-study of low-power CLA adder design

Full Swing Gate Diffusion Input (FS-GDI) methodology is presented. The proposed methodology is applied to a 40nm Carry Look Ahead Adder (CLA). The CLA is implemented mainly using GDI full-swing F1 and F2 gates, which are the counterparts of standard CMOS NAND and NOR gates. A 16-bit GDI CLA was designed in a 40nm low power TSMC process. The CLA, implemented according to the proposed methodology, presents full functionality and robustness under global and local process variations at wide range of supply voltages. Simulation results show 2× area reduction, 5× improvement in dynamic energy dissipation and 4× decrease in leakage, with a slight (24%) degradation in performance, when compared to the CMOS CLA. Advanced design metrics of GDI cells, such as minimum energy point (MEP) operation and minimum leakage vector (MLV), are discussed.

A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability

The need for power-efficient memories that are capable of operating at low supply voltages has led to the development of several alternative bit cell topologies. The majority of the proposed designs are based on the 6T bit cell with the addition of devices and/or peripheral techniques aimed at reducing leakage and enabling read and write functionality at lower operating voltages. In this brief, we propose a reduced transistor count bit cell that is fully functional in the sub-threshold (ST) region of operation. This asymmetric 5T bit cell is operated through a single-ended read and differential write scheme, with an option for operation as a two-port cell with single-ended write. The bit cell's operating scheme provides a non intrusive read operation and improved write margins for robust functionality. In addition, the circuit's asymmetric characteristic provides a low-leakage state with an additional 5X static power improvement over the reduction inherently achieved through voltage lowering. The proposed bit cell was designed and simulated in a 40-nm commercial CMOS process and is shown to be fully operational at ST voltages as low as 400 mV under global and local process variations. At this supply voltage, a 21X static power reduction is achieved, as compared to the industry-standard 6T bit cell, operated at its minimum supply voltage.

Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation

This paper proposes a set of monitor circuits to estimate global process variations in post-silicon. Ring oscillators (ROs) are chosen as monitor circuits where ROs are designed to have enhanced sensitivities to process variations. The proposed technique extracts process parameter variations from RO outputs. An iterative estimation method is also developed to estimate variations correctly under the presence of nonlinearity in RO outputs to process variations. Simulation results show that the proposed circuits are robust against uncertainties such as measurement error. A test chip in a 65-nm process has been fabricated to validate the circuits. Process parameter variations are successfully estimated and verified by applying body bias to the chip. The proposed technique can be used for post-silicon compensation techniques and model-to-hardware correlation.

A Minimum Leakage Quasi-Static RAM Bitcell

As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.

Contact edge roughness metrology in nanostructures: Frequency analysis and variations

► Contact Edge Roughness is evaluated through the analysis of Scanning Electron Microscopy images. ► Emphasis is given on frequency (power spectrum) and spatial (height-heigth correlation function) aspects of CER. ► We find that local process variations affect more CD and CER uncertainty than image magnification and noise smoothing filter. A methodology for the evaluation and characterization of contact edge roughness using top-down images from scanning electron microscope is presented. Emphasis is given on the frequency and spatial aspects of CER and the estimation of the power spectrum and height-height correlation function. We also estimate the contribution of local and global process variations on the CER metrics of real contact holes with nominal critical dimension 50 nm as well as the effects of image magnification and noise smoothing filter. We find that local process variations have stronger contribution to the uncertainty of CD and CER parameters than image magnification and noise smoothing with the latter having the smallest impact.

Principle Hessian Direction-Based Parameter Reduction for Interconnect Networks With Process Variation

As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. To accurately consider both global and local process variations, a large number of random variables (or parameters) have to be incorporated into circuit models. This in turn raises the complexity of the circuit models. In this paper, we propose a principle Hessian direction-based parameter-reduction approach. This new approach relies on the impact of each parameter on circuit performance to decide whether keeping or reducing the parameter. Compared with the existing principle component analysis method, this performance based property provides us a significantly smaller set of parameters after reduction. The experimental results also support our conclusions. In interconnect cases, the proposed method reduces 70% of parameters. In some cases, for example, the mesh circuit in the current paper, the new approach leads to an 85% reduction. We also tested ISCAS benchmarks. In all cases, an average of 53% of reduction is observed with less than 3% error in the mean value and less than 8% error in the variation.

A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

Due to global and local process variations, on-chip SRAM suffers failures at a low supply voltage (VDD). This study proposes a differential data-aware power-supplied D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> AP 8T SRAM cell to address the stability and trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells. Powered by its bitline pair, the proposed 8T cell applies differential data-aware-supplied voltages to its cross-coupled inverters to increase both stability margins for write and half-select accesses. A boosted bitline scheme also improves the read cell current. Two 39 Kb SRAM macros, D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> AP-8T and conventional 8T, with the same peripheral circuits were fabricated on the same testchip with 45 nm and 40 nm processes. The measured VDDmin for the D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> AP-8T macro is 240 mV-200 mV lower than that of the conventional 8T macro across lots, wafers and dies.

Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks

We propose a logic gate leakage model based on transistor stacks, which includes local transistor level process variation parameters along with global process variation parameters and supply and temperature. The stack models include both subthreshold as well as gate leakage and consider the input vector state. We examine cells from an industrial standard cell library and find that most cells can be modeled with simple stacks, which have a linear chain of transistors. However some gates like XOR, Majority or Muxes need complex stacks and we show how these can be modeled. Our experiments show that only 18 different stack models are needed to predict the leakage of all gates in this industrial library. Re-use of the same models for pass transistor logic circuits and multi-finger transistors is also demonstrated. We explicitly include voltage and temperature into the models to support joint estimation of power supply IR drops and leakage currents, as well as enable analysis for dynamic voltage scaling applications. We use artificial neural networks to create unified models which include global and local process variations, supply voltage in the range of V DD /2- V DD and temperature in the range 0-100 °C. These models are very useful for performing statistical leakage analysis of large circuits. Results from the ISCAS'85 benchmark circuits show that neural network based stack models can predict the PDF of leakage current of large circuits across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 7% when compared to SPICE. Further gate level validation has been done for both an industrial 130 nm and 45 nm PTM model files.

Built-In Self-Test of MEMS Accelerometers

A built-in self-test technique that is applicable to symmetric microsystems is described. A combination of existing layout features and additional circuitry is used to make measurements from symmetrically located points. In addition to the normal sense output, self-test outputs are used to detect the presence of layout asymmetry that are caused by local, hard-to-detect defects. Simulation results for an accelerometer reveal that our self-test approach is able to distinguish misbehavior resulting from local defects and global manufacturing process variations. A mathematical model is developed to analyze the efficacy of the differential built-in self-test method in characterization of a wide range of local manufacturing variations affecting different regions of a device and/or wafer. Model predictions are validated by simulation. Specifically, it has been shown that by using a suitable modulation scheme, sensitivity to etch variation along a particular direction is improved by nearly 30%.

Mismatch Modeling and Simulation—A Comprehensive Approach

This article describes a comprehensive approach to mismatch simulation and modeling as needed for integrated circuit design. Local device mismatch as well as global process variations and parameter correlations are regarded. A method for mismatch modeling based on spatial frequencies is described, which enables to overcome insufficiencies of the first order models. Measurement results are presented to demonstrate the achieved modeling precision. All models and methods mentioned here are commercially available in the simulation tool GAME (General Analysis of Mismatch Effects) which is used in the semiconductor industry since 1998.

Monte Carlo optimization of superconducting complementary output switching logic circuits

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix.