Abstract
As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.
Highlights
Throughout the past decade, power dissipation has replaced high performance as the central focus of VLSI design, primarily due to the ever increasing rise in popularity of portable devices
We present a novel 9T Quasi-SRAM bitcell for low-voltage, ultra-low leakage operation
The proposed cell internally cuts off the supply, and the stable states are set by leakage current ratios, resulting in Quasi-Static operation
Summary
Throughout the past decade, power dissipation has replaced high performance as the central focus of VLSI design, primarily due to the ever increasing rise in popularity of portable devices. The proposed cell internally cuts off the supply, and the stable states are set by leakage current ratios, resulting in Quasi-Static operation This is achieved with improved write access time, with a design controlled read access time penalty, and without the need for any additional peripheral. 8kb array of Q-SRAM cell was fabricated in a standard 40nm process and preliminary measurements show full functionality This brief is composed as follows: The cell design and operation methods are shown in Section II; a discussion of cell stability, including the Quasi-Static nature of the cell, is discussed in Section III; Section IV presents the cell implementation and performance figures; and Section V concludes the paper
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