A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

Abstract

Due to global and local process variations, on-chip SRAM suffers failures at a low supply voltage (VDD). This study proposes a differential data-aware power-supplied D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> AP 8T SRAM cell to address the stability and trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells. Powered by its bitline pair, the proposed 8T cell applies differential data-aware-supplied voltages to its cross-coupled inverters to increase both stability margins for write and half-select accesses. A boosted bitline scheme also improves the read cell current. Two 39 Kb SRAM macros, D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> AP-8T and conventional 8T, with the same peripheral circuits were fabricated on the same testchip with 45 nm and 40 nm processes. The measured VDDmin for the D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> AP-8T macro is 240 mV-200 mV lower than that of the conventional 8T macro across lots, wafers and dies.