Global Foundries Research Articles

Dual-Band Waveform Generator With Ultra-Wide Low-Frequency Tuning-Range

This paper presents a novel mixed-signal low-power dual-band square/triangular waveform generator (WFG) chip with a wide low-frequency tuning range for medical bio-electric stimulation therapy. It consists of a relaxation oscillator comprising a hysteresis Schmitt trigger and a timing integrator, along with frequency divider (FD) stages and path selector output for driving an electrode from 16 selectable channels. It was fabricated using Global Foundries 8RF-DM 130-nm CMOS process with a supply voltage of ±1 V for the oscillator and +1 V for logic circuits. The WFG provides an output of around 1.5 $\text{V}_{\textrm {p-p}}$ at a nominal low oscillation frequency of 17 kHz using small-size on-chip passive components of values 10 $\text{k}\Omega $ and 10 pF. The WFG core (band I) can be tuned in the range 6.44–1003 kHz through bias current adjustment, while a lower frequency (band II) in the range 0.1 Hz–502 kHz can be provided digitally through a $\div 2$ stage. The power consumption was only 0.457 mW for the WFG and 2.1 mW for the FD circuit while occupying a total silicon area of only 18 $426~\mu \text{m}^{2}$ .

Evaluation of a front-end ASIC for the readout of PMTs over a large dynamic range

The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of the major detectors for searching for gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit), fabricated with Global Foundry 0.35 μm CMOS technology, has been developed for readout of photomultiplier tubes (PMTs) in the WCDA. This ASIC provides both time and charge measurement of PMT signals. The input charge is converted to a pulse width based on the Time-Over-Threshold (TOT) technique and linear discharge method; as for time measurement, leading edge discrimination is employed. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @1 photoelectron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

Fixed Homography-Based Real-Time SW/HW Image Stitching Engine for Motor Vehicles

In this paper, we propose an efficient architecture for a real-time image stitching engine for vision SoCs found in motor vehicles. To enlarge the obstacle-detection distance and area for safety, we adopt panoramic images from multiple telegraphic cameras. We propose a stitching method based on a fixed homography that is educed from the initial frame of a video sequence and is used to warp all input images without regeneration. Because the fixed homography is generated only once at the initial state, we can calculate it using SW to reduce HW costs. The proposed warping HW engine is based on a linear transform of the pixel positions of warped images and can reduce the computational complexity by 90% or more as compared to a conventional method. A dual-core SW/HW image stitching engine is applied to stitching input frames in parallel to improve the performance by 70% or more as compared to a single-core engine operation. In addition, a dual-core structure is used to detect a failure in state machines using rock-step logic to satisfy the ISO26262 standard. The dual-core SW/HW image stitching engine is fabricated in SoC with 254,968 gate counts using Global Foundry's 65 nm CMOS process. The single-core engine can make panoramic images from three YCbCr 4:2:0 formatted VGA images at 44 frames per second and frequency of 200 MHz without an LCD display.

A low power low noise analog front end for portable healthcare system**Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5–100 Hz) and the achieved noise efficient factor is 6.48.

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum $$S_{21}$$S21 gain of 11.4 dB gain with a $$-$$-3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured $$S_{11}$$S11 and $$S_{12}$$S12 are less than $$-$$-10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.

A High Dynamic Range CMOS Image Sensor With Dual-Exposure Charge Subtraction Scheme

In this paper, we present a CMOS image sensor for star centroid measurement for the application of star trackers. We propose a new capacitive transimpedance amplifier pixel architecture with in-pixel charge subtraction scheme. The pixel is able to achieve high signal-to-noise ratio for dim stars and, at the same time, to avoid saturation for bright stars. A prototype sensor was fabricated using Global Foundry 65-nm mixed-signal CMOS process. Experimental results show that the sensor can achieve 3.8 V/lux·s and 12 dB extension of dynamic range. For the saturated star in conventional method, the centroiding accuracy is improved by over 0.1 pixels after performing charge subtraction.

A 40 GHz 65 nm CMOS Phase-Locked Loop With Optimized Shunt-Peaked Buffer

A 40 GHz phase-locked loop (PLL) with an optimized shunt-peaked buffer is realized in Global Foundries 65 nm CMOS technology. The shunt-peaked buffer placed in the loop eliminates the capacitive loading of the frequency divider and enhances the drive capability. Hence it is possible to use an inductorless frequency divider to reduce potential parasitics in the layout. Thanks to the simplified topology and enhanced output swing, the proposed PLL achieves a good balance among silicon area, output range and phase noise. Measurement shows that the PLL works properly from 39.5 to 41.7 GHz with a phase noise of -102.7, -112, -119 dBc/Hz at 1, 10, and 20 MHz offset from the carrier, respectively. It occupies a chip area of 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including all the testing pads and consumes 87 mW from 1.5 V and 0.8 V supply voltage including the buffers.

Design of a Second-Order Sigma-Delta Modulator

A second-order single bit Sigma - Delta modulator which can be applied to pressure sensor is designed in this paper.The modulator uses switched-capacitor circuit,and the operational amplifier adopts a differential folded-cascode structure with PMOS tube as input. Optimizes the coefficients at the system level design using Simulink tool. The schematic simulation and analysis is by the tools of Spectre and MATLAB with Global Foundry 0.35um CMOS technology. The modulator with oversampling rate of 256 is designed at the 3.3V power supply. Finally, this paper shows the circuit simulation results of the sigma-delta modulator whose signal-noise rate is 103.9dB and resolution is 16.97bits.

Process variation robust current-mode on-chip interconnect signaling scheme

We propose a novel bias circuit, which can help a promising current-mode signaling (CMS) scheme (CMS-bias) enhance the robustness against process variation but consume less energy than the original bias circuit in this scheme. Monte Carlo and process corner analysis are carried out using HSPICE in the Global Foundry 0.18 μm process. Monte Carlo analysis shows that the CMS-bias with proposed bias circuit (CMS-proposed) and the CMS-bias with original circuit (CMS-original) have the same robustness against the variation, but the former offer a 9% reduction in power consumption. The process corner analysis shows that the average power and delay of the CMS-proposed don't change much in different process corners, especially in FS and SF corner. In addition, parameter sensitivity analysis shows that the process variation in long wires has little influence on the delay of the CMS scheme, but the variation in the effective length of MOSFETs influences the performance of the CMS scheme very much.

An Adaptive Integration Time CMOS Image Sensor With Multiple Readout Channels

In this paper, we present an adaptive integration time CMOS image sensor with multiple readout channels for star tracker application. The sensor architecture allows each pixel to have an adaptive integration time. Through cyclically selecting a row of pixels and checking the integration voltage of each pixel, brighter pixels can be marked and readout first. Those dimmer pixels will continue integration until their voltage fall into a window defined by two threshold voltages. Each pixel only consists of five transistors. To improve the readout throughput and hence to reduce the rolling time, a multiple readout channel architecture is proposed. A proof-of-concept 320 × 128-pixel image sensor was implemented using Global Foundries 0.18 μm mixed-signal CMOS process.

A Compact 2.1–39 GHz Self-Biased Low-Noise Amplifier in 65 nm CMOS Technology

A compact self-biased wideband low noise amplifier (LNA) is realized in Global Foundries 65 nm CMOS technology. Wideband input matching characteristic is achieved by placing a series gate inductor and a parallel tuning capacitor in the resistive-feedback network. Combined with the inductive-series peaking technique which further extends the bandwidth, the proposed cascaded three-stage resistive-feedback amplifier obtains a large operating bandwidth which is comparable with the distributed amplifier. Measurement shows that the proposed amplifier achieves a power gain of 10±1.5 dB with I/O return losses better than 8 dB and noise figure ranging from 4.5 to 6.8 dB between 2.1-39 GHz. The maximum output P1dB and input third-order intercept (IIP3) are -6.5 dBm and -5.7 dBm, respectively. The fabricated LNA occupies a silicon area of 0.16 mm2 including all testing pads and draws 17 mA from a 1.5 V power supply.

Centip3De

Process scaling has resulted in an exponential increase of the number of transistors available to designers. Meanwhile, global interconnect has not scaled nearly as well, because global wires scale only in one dimension instead of two, resulting in fewer, high-resistance routing tracks. This paper evaluates the use of three-dimensional (3D) integration to reduce global interconnect by adding multiple layers of silicon with vertical connections between them using through-silicon vias (TSVs). Because global interconnect can be millimeters long, and silicon layers tend to be only tens of microns thick in 3D stacked processes, the power and performance gains by using vertical interconnect can be substantial. To address the thermal issues that arise with 3D integration, this paper also evaluates the use of near-threshold computing---operating the system at a supply voltage just above the threshold voltage of the transistors. Specifically, we will discuss the design and test of Centip3De, a large-scale 3D-stacked near-threshold chip multiprocessor. Centip3De uses Tezzaron's 3D stacking technology in conjunction with Global Foundries' 130 nm process. The Centip3De design comprises 128 ARM Cortex-M3 cores and 256MB of integrated DRAM. Silicon measurements are presented for a 64-core version of the design.&lt;!-- END_PAGE_1 --&gt;

Online-Programming IP Design and Implementation Based on SoC

It is mainly proposed that the design and implementation for an online-programming IP core based on MV10, an SoC, which is an 8-bit MCU having passed the silicon verification with Global Foundry 0.35um mix-signal library in this thesis. The online-programming IP core can write BIN file into the on-chip SRAM, which is mainly controlled by e- rasing state machine and programming state machine, for program debugging with high accuracy-communication and er- ror self-detection. The online-programming IP core proposed in this thesis can also be used in other SoCs.

The Design and Verification of Online-Programming IP Based on SOC

The thesis mainly proposed the design of a reliable online-programming IP core for MV10, a SOC, which is an 8-bit MCU integrated with PWM, ADC, CAN and other function modules. In this thesis the online-programming IP core can write BIN file into the on-chip SRAM for program debugging with high accuracy-communication and error self-detection. The IP core embedded in MV10 has passed the silicon verification with Global Foundry 0.35um mix-signal library. The online-programming IP core proposed in this thesis can also be used in other SOCs.

Compact 50–62 GHz current‐reused low‐noise amplifier with gate‐drain transformer feedback

A compact two-stage 50–62 GHz low-noise amplifier is proposed. Gate-drain transformer feedback and the current-reuse technique are employed to achieve input impedance matching, a low noise figure and low power dissipation simultaneously. The proposed low-noise amplifier, implemented in the Global Foundries 65 nm CMOS process, exhibits a peak gain of 11.8 dB at 58.5 GHz and a minimum noise figure of 5.6 dB. It consumes 15.4 mW from 1.5 V supply with a small area of 0.12 mm2 including all testing pads.

V‐band injection‐locked oscillator with 9 GHz locking range

An injection-locked oscillator (ILO) with a self-biased injection circuit is proposed. By using the series-inductive peaking technique, the efficiency of the signal injection is considerably improved. Implemented in Global Foundries 65 nm bulk CMOS process, the proposed ILO demonstrated a 9 GHz locking range and can operate in 52–71 GHz with the tuning mechanism. Occupying a silicon area of 0.3 mm2, the circuit draws 13 mA from a 1.2 V supply including the output buffers.

3–10 GHz self‐biased resistive‐feedback LNA with inductive source degeneration

A 3–10 GHz self-biased low-noise amplifier (LNA) implemented in Global Foundries 65 nm CMOS process is presented. A novel input-matching network employing the resistive feedback and inductive source degeneration techniques is proposed to achieve the wideband matching as well as low noise figure. The LNA exhibits a power gain of 17 ± 1 dB over 3–10 GHz with noise figure ranging from 3.5 to 4.3 dB. The fabricated LNA occupies an area of 0.15 mm2 and draws 12 mA from 1.2 V power supply.

A NOVEL ULTRA-LOW POWER TWO-TERMINAL ZENER VOLTAGE REFERENCE

A novel ultra-low power two terminal zener voltage reference is designed and implemented. It realizes the concept of using sub-threshold region of the MOSFET to achieve a very low and stable output voltage within a two terminal circuit topology. This proposed voltage reference was fabricated with Global Foundries 0.18-μm CMOS process, consuming only a very small die area of 0.0009 mm2. Experimental results, carried out on five different silicon samples, explicitly show that it can yield a stable output voltage of 0.22 V at room temperature. It achieves an average temperature coefficient of 6.4 ppm/°C across a wide temperature range from 0°C to 150°C with a standard deviation of 2 ppm/°C. Furthermore, it achieves an ultra-low power consumption of 2 μW. The load regulation is 20 mV/V. This simple and innovative two terminal device can be used to provide a very low and constant voltage difference between any two nodes in an analog circuit.

CMOS implementation of a low-power BPSK demodulator for wireless implantable neural command transmission

A new BPSK demodulator was presented. By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator, the circuit structure of the demodulator became simpler and hence its power consumption became lower. Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system. The proposed BPSK demodulator was implemented by Global Foundries 0.35 μm CMOS technology with a 3.3 V power supply. The designed chip area is only 0.07 mm2 and the power consumption is 0.5 mW. The test results show that it can work correctly.

An x86-64 Core in 32 nm SOI CMOS

This paper describes the 32 nm implementation of an AMD x86-64 core. It occupies 9.69 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , contains more than 35 million transistors (excluding L2 cache), and operates at frequencies in excess of 3 GHz. This AMD chip is fabricated in Global Foundries' 32 nm SOI and uses high-K metal gate technology. The process uses dual strain liners and eSiGe (embedded Silicon Germanium) to improve performance. Transistors are fabricated in various threshold voltages and lengths to facilitate performance/leakage tradeoffs. The core incorporates numerous design and power improvements to enable an operating range of 2.5 W to 25 W and a near zero-power gated state, which makes the core well-suited to a broad range of mobile and desktop products including multicore SOC designs.