A Compact 2.1–39 GHz Self-Biased Low-Noise Amplifier in 65 nm CMOS Technology

Abstract

A compact self-biased wideband low noise amplifier (LNA) is realized in Global Foundries 65 nm CMOS technology. Wideband input matching characteristic is achieved by placing a series gate inductor and a parallel tuning capacitor in the resistive-feedback network. Combined with the inductive-series peaking technique which further extends the bandwidth, the proposed cascaded three-stage resistive-feedback amplifier obtains a large operating bandwidth which is comparable with the distributed amplifier. Measurement shows that the proposed amplifier achieves a power gain of 10±1.5 dB with I/O return losses better than 8 dB and noise figure ranging from 4.5 to 6.8 dB between 2.1-39 GHz. The maximum output P1dB and input third-order intercept (IIP3) are -6.5 dBm and -5.7 dBm, respectively. The fabricated LNA occupies a silicon area of 0.16 mm2 including all testing pads and draws 17 mA from a 1.5 V power supply.