Abstract
A compact two-stage 50–62 GHz low-noise amplifier is proposed. Gate-drain transformer feedback and the current-reuse technique are employed to achieve input impedance matching, a low noise figure and low power dissipation simultaneously. The proposed low-noise amplifier, implemented in the Global Foundries 65 nm CMOS process, exhibits a peak gain of 11.8 dB at 58.5 GHz and a minimum noise figure of 5.6 dB. It consumes 15.4 mW from 1.5 V supply with a small area of 0.12 mm2 including all testing pads.
Published Version
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