3.1-10.6 GHz 超寬頻、24-GHz及 V-Band CMOS 低雜訊放大器之設計與實現

Abstract

This thesis aim is to design ultra-wideband, 24-GHz and V-Band CMOS low noise amplifiers. The theme can be divided into three parts： In the first part, a 3.1 ~ 10.6 GHz low noise amplifier is designed for ultra wideband (UWB). Splitting-Load inductive peaking techniques realize a 3.1 ~ 10.6 GHz low noise amplifier. The advantages of the circuit are enhanced bandwidth, good input matching, low noise figure, low cost and reduced chip area for using Splitting-Load inductive peaking technique. In order to achieve small group-delay-variation at the same time, in the output stage we increased the frequency of the dominant pole of the LNA. The shunt peaking was for output matching, there we used three inductors for this work. We design LNA in TSMC 0.18 ?m CMOS technology, incorporated with Splitting-Load inductive the peaking technology so we can complete the above numerous merit. The experimental result shows that we achieve our anticipated characteristic with infer technology was presented in our results. High 12dB gain, S11 below -12 dB, S22 below -11.8 dB, flat noise figure of 3.7~ 4.9 dB and the group-delay-variation only ±17.15 ps form 3.1 to 10.6 GHz. The result shows of power consuming 21.8 mW, and chip area only 0.31 mm2, that the LNA is suitable for SOC. In the second part, the 24-GHz low noise amplifier is implemented for the short-range radar system. In order to obtain a high gain of 20 dB, we used four common source and conjugate matching techniques between each stage. The Current-reuse technique is adopted in the third and the fourth stage to reduce power dissipation. In the fourth stage, to further improve the limitations imposed on the supply voltage, the R-feedback circuit is presented in this work. We design high gain and low noise LNA in TSMC 0.13 ?m CMOS technology. The experimental results showed that the 3 dB bandwidth of 9.4 GHz, flat noise figure of 3.6~ 4.1 dB, consuming power of 18.8 mW, chip area of 0.38 mm2, group-delay-variation of ±12.05 ps, and have figure of merit (FOM) of 3.84, The results show that the LNA is suitable for high resolution radar systems. Final, we design a V-band LNA in TSMC 0.13 ?m CMOS technology. Using the shunt inductor at high frequency, the stray capacitance can be opened with LC circuit. This can enhance power gain and decrease noise figure, only four transistors for this work, the circuit can have 13dB gain and 3dB bandwidth of a 7 GHz, S11 below -11.4 dB, S22 below -8.5 dB, a noise figure of 5.7 dB and good P1-dB of -14 dBm and IIP3 of -3.5 dBm at V-band were achieved, chip area only 0.31 mm2. According to the performance, very suitable conformity in V-band front end receiver.