Process variation robust current-mode on-chip interconnect signaling scheme

Abstract

We propose a novel bias circuit, which can help a promising current-mode signaling (CMS) scheme (CMS-bias) enhance the robustness against process variation but consume less energy than the original bias circuit in this scheme. Monte Carlo and process corner analysis are carried out using HSPICE in the Global Foundry 0.18 μm process. Monte Carlo analysis shows that the CMS-bias with proposed bias circuit (CMS-proposed) and the CMS-bias with original circuit (CMS-original) have the same robustness against the variation, but the former offer a 9% reduction in power consumption. The process corner analysis shows that the average power and delay of the CMS-proposed don't change much in different process corners, especially in FS and SF corner. In addition, parameter sensitivity analysis shows that the process variation in long wires has little influence on the delay of the CMS scheme, but the variation in the effective length of MOSFETs influences the performance of the CMS scheme very much.