GHz Power Amplifier Research Articles

A 60 GHz Power Amplifier with Neutralization Capacitors and Compensation Inductors

In this paper, we present a high power-added efficiency (PAE) and high gain per stage 60 GHz power amplifier (PA). The proposed PA consists of a two-stage common-source amplifier that incorporates neutralization capacitors and compensation inductors to enhance both gain and efficiency. The gain characteristics are analyzed, demonstrating that the proposed design improves both gain and efficiency. Implemented in 65 nm CMOS technology, the PA achieves a saturated output power of 13.4 dBm at 60 GHz, with a maximum PAE of 26.7% from a 1 V supply. The output 1 dB compression point is 10.5 dBm, with a PAE of 16%. The PA occupies a core chip area of 0.094 mm2.

Reliability Assessment of 60-GHz GaN Power Amplifier Under High-Level Input RF Stress

Reliability Assessment of 60-GHz GaN Power Amplifier Under High-Level Input RF Stress

Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler

This paper presents the design and measurements of a 215-252 GHz 40 nm bulk CMOS frequency doubler with a 6.8 dBm deliverable peak output power and a conversion gain of 11.8 dB. The designed chip is composed of a 28.5 dB gain 6-stages 110 GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795 mm2 and shows a total DC power dissipation of 262 mW and DC-RF efficiency of 1.87%.

RapidIP — Automated design of a 220–260 GHz power amplifier in a 130 nm BiCMOS technology

In this work, the automated design of a power amplifier circuit in a 130 nm BiCMOS technology operating in the 220 GHz to 260 GHz frequency range is presented. The design automation process is based on the RapidIP approach, which enables the evaluation, rating and optimisation of thousands of different circuit topologies within only a few minutes. In total 6.13⋅105 optimisation steps and 2.6⋅104 different circuit topologies have been explored within an overall runtime of 23 min. According to post-layout simulations, the amplifier achieves a saturated output power of 9 dBm with a peak power-added efficiency of 2.8% and a 3 dB-bandwidth of 55 GHz.

A 220-GHz InP DHBT power amplifier designed by adaptive impedance inner-stage matching (AIISM) technique

In this paper, we present a 220 GHz power amplifier in a 0.5 μm InP DHBT technology. This power amplifier utilizes six gain stages and four-way power combining. An adaptive impedance inner stage matching (AIISM) technique is proposed to extend the bandwidth. Besides, a co-simulating process is established by collaborating Keysight Advance Design System (ADS) and Ansys High Frequency Structure Simulator (HFSS) to improve the circuit simulation accuracy at terahertz frequencies. The result from the experiment shows that a peak small signal gain of 12.8 dB at 220 GHz. The peak output power of 9.8dBm was measured at 220 GHz and the associated large-signal gain is 7.6 dB. This amplifier occupies a 2.5 mm × 1.9 mm including pads.

A 8–12 GHz power amplifier with high out-of-band rejection

This paper proposes an 8–12 GHz monolithic power amplifier (PA) with high out-of-band rejection. This PA adopts an impedance conversion technique to reduce the Q of the output impedance of the amplifiers for all stages, which is used to achieve broadband matching performance. In addition, the bandpass matching structures and a trap circuit are adopted to effectively suppress out-of-band signals. The proposed PA is fabricated by using a 0.5 μm GaAs pHEMT process. The measurement results show that the PA has an in-band small signal gain of 23 dB ± 0.7 dB, input and output return loss are both better than −14dB, the saturation output power is about 23dBm, the power-added efficiency (PAE) is better than 20 %, and rejection ratios are 65dBc and 51dBc at 3 GHz and 17 GHz respectively. The area is of 2.3mm × 1.1 mm.

A 77 GHz Power Amplifier with 19.1 dBm Peak Output Power in 130 nm SiGe Process.

This article reports a two-stage differential structure power amplifier based on a 130 nm SiGe process operating at 77 GHz. By introducing a tunable capacitor for amplitude and phase balance at the center tap of the secondary coil of the traditional Marchand balun, the balun achieves amplitude imbalance less than 0.5 dB and phase imbalance less than 1 degree within the operating frequency range of 70-85 GHz, which enables the power amplifier to exhibit comparable output power over a wide operating frequency band. The power amplifier, based on a designed 3-bit digital analog convertor (DAC)-controlled base bias current source, exhibits small signal gain fluctuation of less than 5 dB and saturation output power fluctuation of less than 2 dB near the 80 GHz frequency point when the ambient temperature varies in the range of -40 °C to 125 °C. Benefiting from the aforementioned design, the tested single-path differential power amplifier exhibits a small signal gain exceeding 16 dB, a saturation output power exceeding 18 dBm, and a peak saturation output power of 19.1 dBm in the frequency band of 70-85 GHz.

Graphical Approach to Optimization of Maximally Efficient-Gain-Boosted Feedback Amplifiers

It is challenging to design high-gain amplifiers near the maximum oscillation frequency (fmax) of the transistors. This paper presents a comprehensive graphical approach to maximize the gain of feedback amplifiers with maximally efficient gain (GME) conception at near-fmax frequency. The complex gain-plane and the reflection-coefficient-plane are utilized to provide clear insights into both the gain and stability states of the two-port device while boosting GME. An efficient flowchart to synthesize feedback amplifiers is given, which optimizes the GME of a two-port device while ensuring the stability. A 210 GHz power amplifier in 40 nm CMOS was designed and optimized based on the proposed approach. The feedback circuit of the transistor pushes it to become potentially unstable and boosts GME. The measured peak small-signal gain was 10.48 dB at 195.33 GHz. The measured saturation output power and large-signal gain at 210 GHz were 3.04 dBm and 7.08 dB, respectively. The presented method could facilitate terahertz amplifier design.

60 GHz 대역 28 dBm 출력전력을 갖는 GaAs 증가형 pHEMT 전력증폭기 MMIC 설계

A 60 GHz power amplifier (PA) monolithic microwave integrated circuit (MMIC) with +28 dBm output power is designed in an enhancement-mode 0.15 μm GaAs pseudomorphic high-electron-mobility transistor (pHEMT) technology. A two-stage topology and a four-way power combining technique are adopted to achieve a high power gain, high output power, and high linearity. Transistor-level circuit and layout designs are developed, and the circuit performances are verified through three-dimensional electromagnetic simulations. The designed PA MMIC exhibits a saturated output power of +28.4 dBm, output-referred 1-dB gain compression point of +28 dBm, power gain of +8.1 dB, and power added efficiency of 29.3 %. S-parameter simulations show that the small-signal gain is +8.1 dB, and the operating bandwidth is between 55.7 and 63.1 GHz, with a fractional bandwidth of 12.3 %. The supply voltages are 4 V for the drain and 0.6 V for the gate. The positive-only supply voltages resulting from the enhancement-mode pHEMT simplify the supply voltage network compared with the conventional depletion-mode pHEMT design. The layout die size of the PA MMIC is 1.99×1.62 mm2, and the power density performance of 214 mW/mm2 is satisfactory.

A 62-GHz High-Efficiency Power Amplifier With Modulation Capability via Back-Gate in 22-nm FD-SOI

This letter presents a feasibility study for a 62 GHz power amplifier (PA) in a 22 nm CMOS technology with integrated data modulation via the back-gate. The proposed PA consists of two pseudo-differential cascode stages, and provides a peak gain of 23.3 dB, a Psat of 13.6 dBm and a peak PAE of 28.3%. The PA consumes 96 mW from a 2 V VDD at its saturation. Thanks to the transistor back-gate, the PA can be dynamically switched on and off by increasing the threshold voltage through the back-gate. This avoids AC ground, gain and stability problems caused by conventional front-gate switching. In off-mode it draws 2.5% of its peak DC power. Rise-and fall-times of 1 ns were measured. The possibility of back-gate based modulation was experimentally demonstrated, showing that the PA can be used as a single device transmitter. Compared to previously reported works the PA shows one of the highest PAE and excellent linearity. To the best knowledge of the authors, this is the first investigation of a 60 GHz PA with data modulation via the back-gate.

A Ka-band Power Amplifier with On-chip Power Detector in 0.15 μm GaAs pHEMT Technology

A three stage 28 GHz power amplifier (PA) with on-chip power detector is presented. A 0.15 μm GaAs pHEMT process is used to implement the power amplifier. The chip size is 2.09 mm × 1.28 mm including the on-chip power detector and I/O pads. The PA die chip is attached on a commercial open cavity QFN package to evaluate the performances in surface mount use. The on-chip power detector is designed with directional coupler using diode rectifier to monitor available output power from the PA. The detector output voltage is very coherent to the output power in the operation frequency from 26.6 GHz to 29.2 GHz, where the deviation of the detector output voltage is lower than ± 3.7 % up to 27.4 dBm output power. The output PSUB1dB/SUB is over than 26.9 dBm, saturated output power is over 27.4 dBm, and the PAESUBmax/SUB is 25~30 % across the operation frequency.

A four‐element 132–140 GHz PA array with 29.7 dBm EIRP in 0.13‐µm SiGe technology

AbstractThis paper presents a 132–140 GHz power amplifier (PA) array in 0.13‐µm SiGe BiCMOS technology. The four dielectric‐loaded end‐fire antennas are integrated with the PA array on chip. With the absence of the lossy power combining networks at the output, the presented PA array achieves a measured maximal effective isotropic radiated power of 29.7 dBm. The array size is only 6.14 × 2.49 mm2 and consumes 5.16 W from a single 4 V DC supply.

Experimental Investigation of Relationship between Humidity Conditions and Degradation of Key Specifications of 0.1-1.2 GHz PA in 0.18 μm CMOS.

The specification of power amplifiers (PA) is closely related to humidity variation, and few reports on the humidity properties of PA are available in the literature. Therefore, an experimental study of PA specifications was conducted under different humidity conditions to elucidate the relationship between the degradation of PA specifications and humidity conditions. This paper studies and provides results of the degradation of a PA subjected to different humidity levels. The experimental results show that the S21 and output power decrease with the increase in humidity. The main cause of this degradation is the decrease in oxide capacitance and increase in threshold voltage with increasing humidity, resulting in a reduction of transconductance and an increase in on-resistance. The results of this study can guide designers in designing compensation circuits to achieve some degree of compensation for the degradation of PA specifications.

Design of Continuous Class-F Mode Power Amplifier with High Gain Flatness

In this letter, a novel RF power amplifier (PA) with high gain flatness and high efficiency operating in continuous Class-F mode is introduced. Since most continuous Class-F PAs can’t meet the requirement of high gain flatness, a new structure which can achieve high gain flatness is presented. A 1.7-2.5GHz PA is designed, which uses CGH40010F GaN device. Simulation results show that the drain efficiency (DE) of the continuous Class-F PA is between 69% and 79%, output power is more than 41dBm across the whole bandwidth. Gain is between 11dB and 11.8dB, and gain flatness is 0.8dB.

A Compact 60GHz Power Amplifier in 65nm CMOS Technology

A compact 60GHz power amplifier chip in 65nm CMOS technology of three-stage common source structure is presented. The first two amplifiers offer sufficient gain to pre-amplify the small input power. The third stage amplifier uses two sets of differential pairs to achieve power synthesis. On-chip transformer coupling is adopted to realize inter-stage impedance matching as well as input and output matching. The compact structure of on-chip transformer can reduce the chip size and improve the integration degree. The measured small signal gain at 60GHz of 22.3dB, the saturation power of 20.2dBm, the output P-1dB of 17.3dBm, the PAE of 14%, and the core area is 0.19mm2. The power amplifier can be used in high-speed short-range wireless communication system to enhance communication data transmission capacity.

On‐demand digital predistortion for broadband transmitters with carrier aggregation

AbstractThis paper proposes a single and dual‐band compatible digital predistortion (SDBC‐DPD) for broadband transmitters with carrier aggregation. Since complicated spectrum scheduling, the stimuli of the power amplifiers (PAs) can be single‐band and dual‐band. The proposed SDBC‐DPD scheme can well linearize a dual‐band signal in a conventional 1‐D‐DPD way utilizing a spectrum splicing and segmentation method. A series of experiments were carried out on a dual‐band test bench based on a 3.0–4.0 GHz PA. The stimuli with different bandwidths and sampling rates were used in the experiments. Measurement results show that the SDBC‐DPD can well mitigate the nonlinearity in the dual‐band signals and needs a much lower sampling rate for model identification.

An E-Band SiGe High Efficiency, High Harmonic Suppression Amplifier Multiplier Chain With Wide Temperature Operating Range

This paper presents a monolithically integrated E-band amplifier multiplier chain (AMC) developed in 130 nm SiGe BiCMOS process. This E-band AMC is composed of a 25 GHz 1:1 power divider, two 25 GHz driver amplifiers (DA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1,2</sub> ), a 75 GHz passive frequency tripler, and a 75 GHz power amplifier (PA). By applying a bypass tuning capacitor based power enhancing technique in the single-ended DA and PA, the output power and power-added-efficiency (PAE) of the AMC have been effectively improved. Benefiting from the proposed passive tripler core with second harmonic suppression function, and the impedance matching network with frequency selection characteristics, the AMC presents better harmonic suppression performance compared with the conventional topology. The bias circuits with temperature compensation are applied to the DA and PA to ensure the performance of the AMC when the temperature changes. The AMC has a measured output power exceeding 0 dBm in the entire E-band frequency range with a peak output power of 10.9 dBm at 77 GHz, and exhibits a record PAE of 8.25 %. Within the 3 dB operating frequency range from 69 to 87 GHz, the rejection of fundamental and second harmonics are better than 33.5 dB. The AMC can work properly between −40°C and 125 °C with the proposed temperature compensation bias circuits.

A Compact 140-GHz CMOS Power Amplifier With 10.5-dBm Output Power and 27.6-dB Power Gain Supporting up to 128-QAM Modulation

A compact 140 GHz power amplifier (PA) with employed multi-layer stacked transformer (MLST) matching network is implemented in a 65-nm CMOS process. The employed MLST matching network adopts two metal layers as the primary coil and one single layer as the secondary coil to increase the coupling factor and decrease the insertion loss (IL) of the matching network at D-band frequency range. Besides, a gain-boosting unit is further introduced in the first stage of the PA to enhance the power gain. The proposed 140 GHz PA achieves a measured PAE of 6.9%, a Psat of 10.5 dBm and an OP1dB of 7.03 dBm with a maximum power gain of 27.6 dB when the gain-boosting unit turns off. By turning on the gain-boosting unit, the power gain managed to increase from 27.6 dB to 31 dB with stability. Furthermore, modulation measurement shows that the proposed D-band PA supports 24 Gb/s 64-QAM and 11.2 Gb/s 128-QAM modulated signals with error vector magnitudes (EVM) of -23.1 dB/-22.87 dB at the output power of 7 dBm, respectively. The core chip area and dc power consumption of the PA are only 0.0275 mm and 170 mW.

A 54–68 GHz Power Amplifier With Improved Linearity and Efficiency in 40 nm CMOS

This brief presents a 54–68 GHz two-stage power amplifier (PA) with linearity and efficiency enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded common-source (CS) structure with a shunt RC feedback to maximize the gain and minimize the DC power consumption to boost the linearity and efficiency, while the second stage is a cascode structure with two built-in linearizers to enhance the linearity much further. Based on the proposed structure, the fabricated PA exhibits measured output of 1-dB compression point, saturated output power, power added efficiency (PAE) and AM-PM distortion of +14 dBm, +15 dBm, 20% and 8 degrees, respectively. In addition, the proposed CMOS PA achieves high and flat power gain of 14 dB with ripple less than 1.5 dB through the operating 54—68 GHz frequency band while consuming only 110 mW.

Design and analysis of a high-performance 90-101 GHz CMOS power amplifier

ABSTRACT A three-stage four–way 90–101 GHz power amplifier (PA) on 90 nm CMOS is reported. The PA consists of a meandrous four-way Wilkinson power divider, and common-source (CS) input and gain stages with inductive shunt-shunt feedback, followed by four-way CS output stage using a compact four-way current combiner. Wideband π-match inter-stage networks are used for broadband impedance and power matching. An LC input network (constituting a series capacitor, a parallel inductor, and an inductive shunt-shunt feedback) is used to convert the input impedance of the input-stage transistors to 50 Ω. This is the way to attain impedance matching at the outputs of the four-way Wilkinson power divider. Besides, an LC output network (constituting a series LC and a parallel inductor) is used to convert the 50 Ω load to the needed series RL load of the four-way current combiner. As a whole, the output-stage transistors operated at the maximal output power (Pout) and power-added efficiency (PAE). At 94 GHz, the PA attains gain of 20.1 dB, saturated Pout (Psat) of 17.5 dBm, and maximal PAE (PAEmax) of 17.7%, one of the best results ever reported for W-band CMOS PAs. The remarkable performance of the CMOS PA reveals its potential for 94 GHz radar systems.