GHz Power Amplifier Research Articles

A Wideband, Dual-Path, Millimeter-Wave Power Amplifier With 20 dBm Output Power and PAE Above 15% in 130 nm SiGe-BiCMOS

A frequency-scalable, three-stage, transformer-coupled millimeter-wave power amplifier (PA) is implemented in 130 nm SiGe-BiCMOS. Differential common-base gain stages extend collector-emitter breakdown voltage beyond 3 V, while collector-emitter neutralization increases reverse isolation and stability. Monolithic self-shielded transformers designed for low insertion loss and compact dimensions on-chip include: a 2:4 input power splitter, a 4:1 output balun combiner and inter-stage coupling transformers. The balun combiner and fully-differential splitter are compensated for imbalances caused by parasitic interwinding capacitance, and simulations predict better than 3% uniformity between reflected port-to-port impedances at 60 GHz. Simulated impedance uniformity is within 6% from 55-65 GHz, and insertion loss of the 0.015 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> combiner prototypes at 60 GHz is below 1 dB. The 0.72 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 60 GHz-band PA realizes a measured peak small-signal gain higher than 20 dB with over 10 GHz 3 dB bandwidth. Reverse isolation is better than 51 dB from 50-65 GHz and the PA is unconditionally stable. It consumes 353 mW (quiescent) from a 1.8 V supply and the active area is 0.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Maximum output power and peak power-added efficiency (PAE) are 20.1 dBm and 18% at 62 GHz, respectively. An up-banded 79-87.5 GHz PA is also implemented to verify frequency scalability of the design. The 0.23 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area 79 GHz PA prototype produces 18 dBm saturated output power and 9% peak-PAE at 84 GHz from a 2.5 V supply.

60 GHz CMOS power amplifier with P sat of 11.4 dBm and PAE of 15.8%

A 60 GHz power amplifier (PA) for a direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises three cascaded common-source stages with inductive load and inter-stage matching. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, a miniature low-loss LC power divider and a combiner are used. This in turn results in further Psat and PAE enhancement. Over the 57–64 GHz band of interest, the PA consumes 44.4 mW and achieves a power gain (S21) of 12.04±1 dB. At 60 GHz, the PA achieves Psat of 11.4 mW and a maximum PAE of 15.8%. To the authors’ knowledge, this is the best PAE ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60 GHz short-range communication systems.

A 60 GHz power amplifier using lange couplers in GaAS 0.15 μm pHEMT process

This letter proposes a 60 GHz power amplifier (PA) fabricated in GaAs 0.15μm pHEMT process technology.A three-stage topology with Lange couplers is adopted. The measured results show that the proposed PA achieves a gain of 23 dB and a saturated output power of 14.46 dBm at 63.4 GHz, and its peak power-added efficiency is 6.9%. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2150–2153, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27015

Design-in-Reliable Millimeter-Wave Power Amplifiers in a 65-nm CMOS Process

A hot carrier ageing model previously validated on a one-stage 60-GHz power amplifier (PA) is demonstrated to be able to predict the degradation of the characteristic parameters for multistage high-performance millimeter-wave (mmW) PAs. The increase in the threshold voltage, the decrease in the transconductance, and the output conductance of the MOSFETs caused by hot carriers leads to a degradation in performance of the PAs. Consequently, by using this ageing model, the mmW PA lifetime can be extracted. A new PA is then designed, taking into account the ageing effects, and is shown to be reliable during ten years. This amplifier exhibits a power gain of 20 dB, an output 1-dB compression point of 12.5 dBm with 6.6% power-added efficiency, and a saturated output power of 16 dBm at 60 GHz.

다중 톤 신호의 통계적 특성 확보를 통한 광대역 신호 증폭기의 인접 채널 간섭 분석

본 논문에서는 광대역 무선 신호를 증폭하는 전력증폭기의 성능 테스트 시 인접 채널 간섭(ACLR) 특성을 측정하는 데 있어서, 효과적인 다중 톤 생성을 활용한 테스트 방안에 관하여 연구하였다. 그 동안 단일 주파수 정현파 신호를 테스트에 활용하는 경우 신호가 복잡해짐에 따라 오차가 증가하는 문제점이 있기에, 실제 변조 신호와의 측정 오차를 최소화하도록 다중 톤 신호를 설계하는 방식을 제안하였다. 제안된 다중 톤은 시간 축에서의 유사성을 확보하는 방식으로 설계되어 기존의 다중 톤 생성 방식 대비 더욱 적은 수의 톤으로 정확한 결과를 얻을 수 있다. 이의 검증을 위하여 802.11a 규격의 기저 대역 복소 신호를 다중 톤 신호로 대체하였으며, 이를 전력증폭기 성능 검증에 활용하였다. 그 결과, N=10 이상의 톤 수를 확보하는 경우 3차, 5차 비선형성에 의한 ACLR 특성이 실제 신호 활용한 경우와 1 dB 이하의 오차를 나타내었다. In this paper, a design method of multi-tone signals for the measurement of adjacent-channel power-ratios on power amplifiers is suggested. Because most tests for power amplifiers in production are performed with single-tone signals, its testing accuracy is not guaranteed as the signal complexity increases. Therefore, the application of multi-tone signals to the testing is suggested by optimized complex coefficients of each tones for the best statistical similarity to the original modulated signal. From the verification, a 802.11a signal was replaced with a multi-tone signal of N=10, with the complex coefficients generated by the suggested method. The resulting measurements on the ACLR of 2.4 GHz power amplifier showed successful accuracy of less than 1 dB discrepancy.

A 60-GHz 1-V Supply Band-Tunable Power Amplifier in 65-nm CMOS

This brief presents the design of a band-tunable 60-GHz CMOS power amplifier using 65-nm standard CMOS technology. To achieve high gain and PAE over the whole 7-GHz frequency band, this amplifier utilizes a differential band switching circuit to tune the center frequency to the channel in use, whereas high-Q transformer matching and deep-neutralized differential pairs are employed to achieve high gain and PAE in a narrow bandwidth. The amplifier achieves saturated output power of 12.3 dBm and peak PAE of 20.4% with a 1-V supply and a 63-mA current. The peak gain is 17.1 dB at 59 GHz and 16.2 dB at 53.5 GHz for the two different frequency bands, respectively.

Enhanced performance of a 60-GHz power amplifier by using slow-wave transmission lines in 40 nm CMOS technology

This paper shows the contribution of slow-wave coplanar waveguides on the performance of power amplifiers operating at millimeter-wave frequencies in CMOS-integrated technologies. These transmission lines present a quality factor Q two to three times higher than that of the conventional microstrip lines at the same characteristic impedance. To demonstrate the contribution of the slow-wave transmission lines on integrated millimeter-wave amplifiers performance, two Class-A single-stage power amplifiers (PA) operating at 60 GHz were designed in standard 40 nm CMOS technology. One of the power amplifiers incorporates only the microstrip lines, whereas slow-wave coplanar transmission lines are considered in the other one. Both amplifiers are biased in Class-A operation, drawing, respectively, 22 and 23 mA from 1.2 V supply. Compared to the power amplifier using conventional microstrip transmission lines, the one implemented with slow-wave transmission lines shows improved performances in terms of gain (5.6 dB against 3.3 dB), 1 dB output compression point (OCP1dB: 7 dBm against 5 dBm), saturated output power (Psat: &gt;10 and 8 dBm, respectively), power-added efficiency (PAE: 16% instead of 6%), and die area without pads (Sdie: 0.059 mm2 against 0.069 mm2).

A 3.4–3.6 GHz power amplifier in an InGaP/GaAs HBT

This paper presents a 3.4–3.6 GHz power amplifier (PA) designed and implemented in InGaP/GaAs HBT technology. By optimizing the off-chip output matching network and designing an extra input-matching circuit on the PCB, several problems are resolved, such as resonant frequency point migration, worse matching and lower gain caused by parasitics inside and outside of the chip. Under Vcc = 4.3 V and Vbias = 3.3 V, a P1dB of 27.1 dBm has been measured at 3.4 GHz with a PAE of 25.8%, the 2nd and 3rd harmonics are −64 dBc and −51 dBc, respectively. In addition, this PA shows a linear gain more than 28 dB with S11 < −12.4 dB and S22 < −7.4 dB in 3.4–3.6 GHz band.

A 60 GHz Tunable Output Profile Power Amplifier in 65 nm CMOS

A fully integrated three-stage 60 GHz power amplifier with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region. At a supply voltage of 1 V, the fully differential amplifier achieves a linear gain of 15 dB and occupies a compact area of 0.056 mm2. It achieves a minimal Psat-P1dB separation of 0.6 dB by extending the P1dB by 8.5 dB. To our best knowledge, this is the smallest Psat-P1dB separation reported to date. With on-chip phase compensation, the output phase variation is reduced by 57%.

High gain and high efficiency CMOS power amplifier using multiple design techniques

A 60 GHz power amplifier (PA) using standard 90 nm CMOS technology is presented. This PA has power gain greater than 30 dB and 18.3% peak power added efficiency (PAE) under 2 V supply voltage. The parallel arrayed cascode power cells, which have a small number of fingers, are combined by the delay line to produce high gain and high PAE. Common gate inductors are inserted as gain booster circuits. A diode lineariser (DL) is adopted for increasing PAE and output P1dB (OP1dB). The measured saturation power is 13.2 dBm with its 11.5 dBm OP1dB. The measure power gain is above 25 dB over the whole frequency range (56–65 GHz). Due to the DL, the measured PAE exceeds 14% at the OP1dB power. This is believed to be the first CMOS PA having such high power gain and PAE.

A 60 GHz 14 dBm power amplifier with a transformer-based power combiner in 65 nm CMOS

A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based power combiner to sum the output power from two unit PAs. Each unit PA uses transformer-coupled two-stage differential cascode topology. The differential cascode PA is able to increase the output power and ensure stability. The transformer-based passives enable a compact layout with the PA core area of only 0.3 mm2. The PA achieves a peak power gain of 10.2 dB with 3-dB bandwidth of 9 GHz. The measured saturated output power is 14.8 dBm with a peak power-added efficiency (PAE) of 7.2%. The reverse isolation is smaller than −33 dB from 25 to 65 GHz. The PA consumes a quiescent current of 143 mA from a 1.6 V supply.

A 2.4 GHz power amplifier in 0.35 μm SiGe BiCMOS

This paper presents a 2.4 GHz power amplifier (PA) designed and implemented in 0.35 μm SiGe BiCMOS technology. Instead of chip grounding through PCB vias, a metal plate with a mesa connecting ground is designed to decrease the parasitics in the PCB, improving the stability and the gain of the circuit. In addition, a low-pass network for output matching is designed to improve the linearity and power capability. At 2.4 GHz, a P1dB of 15.7 dBm has been measured, and the small signal gain is 27.6 dB with S11 < −7 dB and S22 < −15 dB.

A CPW-Based 77 GHz Power Amplifier with Cascode Structure Using a 130 nm In0.88GaP/In0.4AlAs/In0.4GaAs mHEMTs

In this paper, we present a CPW-based 77 GHz 3-stage power amplifier MMIC for automotive radar systems. The power amplifier MMIC has been realized using a 130 nm <TEX>$In_{0.88}$</TEX>GaP/<TEX>$In_{0.4}$</TEX>AlAs/<TEX>$In_{0.4}$</TEX>GaAs metamorphic high-electron mobility transistors(mHEMTs) technology and an output stage with a cascode configuration. This produced a good output power and gain performance at 77 GHz. The fabricated power amplifier MMIC exhibited a small-signal gain of 18 dB, an output power of 17 dBm and 9 % power added efficiency(PAE) at 77 GHz with a total gate width of 800 <TEX>${\mu}m$</TEX> in the output stage. These performances could be useful to low-cost and small-sized components for 77 GHz automotive radar systems.

Microwave dynamic large signal waveform characterization of advanced InGaP HBT for power amplifiers

In wireless mobile communications and wireless local area networks (WLAN), advanced InGaP HBT with power amplifiers are key components. In this paper, the microwave large signal dynamic waveform characteristics of an advanced InGaP HBT are investigated experimentally for 5.8 GHz power amplifier applications. The microwave large signal waveform distortions at various input power levels, especially at large signal level, are investigated and the reasons are analyzed. The output power saturation is also explained. These analyses will be useful for power amplifier designs.

Single-Chip Frequency Multiplier Chains for Millimeter-Wave Signal Generation

Two single-chip frequency multiplier chains targeting 118 and 183 GHz output frequencies are presented. The chips are fabricated in a 0.1 ?m GaAs metamorphic high electron-mobility transistor process. The D-band frequency doubler chain covers 110 to 130 GHz with peak output power of 5 dBm. The chip requires 2 dBm input power and consumes only 65 mW of dc power. The signal at the fundamental frequency is suppressed more than 25 dB compared to the desired output signal over the band of interest. The G-band frequency sextupler (×6) chain covers 155 to 195 GHz with 0 dBm peak output power and requires 6.5 dBm input power and 92.5 mW dc power. The input signal to the multiplier chain can be reduced to 4 dBm while the output power drops only by 0.5 dB. The unwanted harmonics are suppressed more than 30 dB compared to the desired signal. An additional 183 GHz power amplifier is presented to be used after the ×6 frequency multiplier chain if higher output power is required. The amplifier delivers 5 dBm output power with a small-signal gain of 9 dB from 155 to 195 GHz. The impedance matching networks are realized using coupled transmission lines which is shown to be a scalable and straightforward structure to use in amplifier design. Microstrip transmission lines are used in all the designs.

Design Approach to CMOS Based Class-E and Class-F Power Amplifiers

This paper presents the design flow for an integrated power amplifier. The flow is presented as a software routine. For a given set of amplifier specifications and CMOS process parameters, the routine computes the passive component values for a Class-E or Class-F based power amplifier. The routine includes the matching network for standard impedance loads. The routine also provides its user with a spiral inductor search algorithm, which can be used to generate layouts of inductors with Q-factors optimised at a desired frequency. For a typical power amplifier design case where several amplifiers are designed for application over different channels, the routine presented in this paper contributes by streamlining the design flow. The operation of the software routine was demonstrated by simulations in Austriamicrosystems 0.35 μm single-supply process for a 14 dBm, 2.4 GHz power amplifier design.

A High Gain 77 GHz Power Amplifier Operating at 0.7 V Based on 90 nm CMOS Technology

A 77 GHz 90 nm CMOS power amplifier (PA) demonstrates a gain of 17.4 dB and a saturated output power of 5.8 dBm at a low supply voltage of 0.7 V. To take care of hot-carrier injection degradation, the supply voltage is reduced from a standard voltage of 1.0 V. The saturated output power is increased to 9.4 dBm with a linear gain of 20.6 dB at 1.0 V operation. The amplifier consists of three-stage common-source nMOSFETs with gate widths of 40, 80, and 160 mum. To our best knowledge, the developed PA shows the highest gain ever achieved for W-band CMOS amplifier. The measured temperature characteristics suggest that a simple compensation technique is possible by gate bias control.

Characterisation, analysis and injection of two-tone third-order intermodulation products in an amplifier

A new mathematical description of the relationship between injected and output third-order intermodulation (IM3), to predict the injection signals required for predistortion correction of a power amplifier (PA), without manual optimisation is presented. A new concept of interactions and an iteration algorithm are also presented in order to improve this technique. The method is demonstrated with a commercial 2 GHz PA driven hard in a two-tone test with a range of input power and tone-spacing. The measurement results show that IM3 in a two-tone test can be suppressed by at least 60 dB, when the interactions between the upper and lower IM3 generation and the correction process are properly accounted for. The technique can deal with memory effects by cancelling unequal upper and lower sidebands.

Hybrid predistortion to compensate third- and fifth-order intermodulation of a 2 GHz power amplifier using cuber predistortion and second harmonics injection

A new circuit construction technique that actively utilises second harmonics injection (HI) to realise fifth-order predistortion (PD) for power amplifiers (PAs) with memoryless AM/AM and AM/PM conversions is proposed. Applying a combination of the proposed technique and cuber predistortion (CPD) to third-order distortion yields the simultaneous compensation of both third- and fifth-order intermodulation distortion (IM3 and IM5); capabilities are not possible with the conventional third-order PD approach. Since the proposed method can be implemented as a simple analogue circuit, it betters compactness and lowers cost. In order to derive the PA bias condition at which second HI works most effectively, a complex power series nonlinear model that allows both amplitude and phase nonlinearities to be dealt with simultaneously is used. To confirm the author's compensation theory, a 2'GHz band PA and a hybrid lineariser that employs second HI and CPD are fabricated and experiments are performed. About a 20'dB simultaneous reduction in IM3 and IM5 is achieved with the two-tone test. A W-CDMA one-carrier test is also conducted to verify the improvement in adjacent channel leakage power ratio compared with CPD only.

Metamorphic HEMT MMICs and Modules for Use in a High-Bandwidth 210 GHz Radar

In this paper, we present the development of advanced W-band and G-band millimeter-wave monolithic integrated circuits (MMICs) and modules for use in a high-resolution radar system operating at 210 GHz. A W-band frequency multiplier by six as well as a subharmonically pumped 210 GHz dual-gate field-effect transistor (FET) mixer and a 105 GHz power amplifier circuit have been successfully realized using our 0.1 mum InAlAs/InGaAs based depletion-type metamorphic high electron mobility transistor (mHEMT) technology in combination with grounded coplanar circuit topology (GCPW). Additionally, a 210 GHz low-noise amplifier MMIC was fabricated using our advanced 0.05 mum mHEMT technology. To package the circuits, a set of waveguide-to-microstrip transitions has been realized on 50 mum thick quartz substrates, covering the frequency range between 75 and 220 GHz. The presented millimeter-wave components were developed for use in a novel 210 GHz radar demonstrator COBRA-210, which delivers an instantaneous bandwidth of 8 GHz and an outstanding spatial resolution of 1.8 cm.