GHz Power Amplifier Research Articles

Digitally-Compensated Wideband 60 GHz Test-Bed for Power Amplifier Predistortion Experiments.

Millimeter waves will play an important role in communication systems in the near future. On the one hand, the bandwidths available at millimeter-wave frequencies allow for elevated data rates, but on the other hand, the wide bandwidth accentuates the effects of wireless front-end impairments on transmitted waveforms and makes their compensation more difficult. Research into front-end impairment compensation in millimeter-wave frequency bands is currently being carried out, mainly using expensive laboratory setups consisting of universal signal generators, spectral analyzers and high-speed oscilloscopes. This paper presents a detailed description of an in-house built MATLAB-controlled 60 GHz measurement test-bed developed using relatively inexpensive hardware components that are available on the market and equipped with digital compensation for the most critical front-end impairments, including the digital predistortion of the power amplifier. It also demonstrates the potential of digital predistortion linearization on two distinct 60 GHz power amplifiers: one integrated in a direct-conversion transceiver and an external one with 24 dBm output power.

A 65nm CMOS 60 GHz Class F-E Power Amplifier for WPAN Applications

This work presents a two-stage 60 GHz Power Amplifier designed in a 65nm CMOS technology dedicated to low cost Wireless Personal Area Network (WPAN) applications. In order to provide a high efficiency operation, the PA is based on a Class E power stage. A Class F driver stage is also designed to provide a square waveform signal to the Class-E power stage. To realize the output networks of both driver and power stage at 60 GHz, distributed elements are used instead of lumped elements. The post-layout simulation results show a saturated output power of 15 dBm with a peak PAE of 26% at 60 GHz. It achieves a gain of 15dB at 60 GHz.

A 52–58 GHz Power Amplifier With 18.6-dBm Saturated Output Power for Space Applications

This brief presents a 52–58 GHz power amplifier (PA) with constant output power across the entire band. A new topology based on the impedance transformation of transmission lines was adopted as the inter-stage matching network. Compared with the conventional 2-section LC matching topology, our approach reduced the matching loss by 1.5 dB at 54 GHz. Such topology made the design capable of operating at a frequency close to 80% of the unit-current-gain cut-off frequency ( $f_{T}$ ) specified by the device technology. Additionally, stacked-FET was adopted as the power stage for the output power enhancement in a broadband sense. Implemented in the commercially available 0.15- $\boldsymbol{\mu }\text{m}$ GaAs pseudomorphic high-electron-mobility transistor (pHEMT) process, the 2-stage PA demonstrated a small-signal gain of 14.7 dB, a saturated output power ( $P_{sat}$ ) of 18.6 dBm, and a maximum power-added-efficiency (PAE) of 18.2% at 54 GHz.

Efficient 60-GHz Power Amplifier With Adaptive AM-AM and AM-PM Distortions Compensation in 65-nm CMOS Process

This article presents a 60-GHz CMOS power amplifier (PA) with an adaptive impedance-compensation linearizer in the 65-nm CMOS process. The proposed linearizer adaptively provides resistance and capacitance that vary appropriately with input power, enabling amplitude-to-amplitude modulation (AM-AM) and amplitude-to-phase modulation (AM-PM) distortions to be compensated simultaneously. The fabricated PA with linearizer on achieves a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB of 12.3 dBm and a peak power-added efficiency (PAE) of 15.6% at such P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB, which demonstrate improvements of 2.8 dB and 6.8%, respectively, compared with the PA with linearizer off. The PA also achieves the peak gain of 31.0 dB, peak saturated power (PSAT) of 15.0 dBm, and peak PAEmax of 22.7%. In addition, the AM-AM distortion at 6-dB output back-off (OBO) is less than 0.1 dB, and the AM-PM distortion at P1 dB is less than 1.5° in the overall 3-dB frequency band. The improvements in both the AM-AM and AM-PM signals lead to a 1.7-dB improvement in OBO at third-order intermodulated distortion of -25 dBc without adding to power consumption.

A 28 GHz Linear Power Amplifier Based on CPW Matching Networks with Series-Connected DC-Blocking Capacitors

In this paper, the influence of the DC-blocking capacitors leveraged in coplanar waveguide (CPW) matching networks is studied. CPW matching networks with series-connected DC-blocking capacitors are less sensitive to capacitance and are adopted in a 28 GHz power amplifier (PA). The PA targeting fifth-generation (5G) phased array is developed in 90 nm silicon-on-insulator complementary-metal-oxide-semiconductor (SOI CMOS) technology. A stacked field-effect-transistor (FET) architecture is elected in the output stage to boost the output power and reduce the die area. The PA with a core area of 0.31 mm2 demonstrates a maximum small signal gain of 13.7 dB and a −3 dB bandwidth of 6.3 GHz (22.9–29.2 GHz). The PA achieves a measured saturated output power (Psat) of 14.4 dBm and a peak power added efficiency (PAE) of 25% for continuous wave signals. At 24/25.6/28 GHz, the PA achieves +7.87/+9.16/+10.7 dBm measured output power and 6.21%/8.11%/10.17% PAE at −25 dBc error vector magnitude(EVM) for a 250 MHz-wide 64-quadrature amplitude modulation (64-QAM). The developed linear PA provides a great potential for low-cost 5G phased array transceivers.

A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications

A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology for milimeter wave applications is reported. Maximizing the power added efficiency (PAE) and output power are achieved by optimize the circuit with power divider and cascade configuration. In addition, reverse body bias is also employed for realizing excellent PAE and power consumption. A three stage CMOS PA with power combiner is designed and simulated. The simulation results show that the proposed PA consumes 62.56 mW and power gain (S21) of 8.08 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 12.62 dBm and maximum PAE of 23.74% with output 1-dB compression point (OP1dB) 10.85 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.

Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity

We present the possibility of a complementary metal-oxide semiconductor (CMOS) power amplifier (PA) using a driver stage composed of p-channel metal oxide semiconductor (PMOS) to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to the CMOS PA. By biasing the common-source transistor of the driver stage at the subthreshold region, we obtain a gm3 value with a positive sign to cancel out the negative gm3 of the power stage, thereby enhancing the linearity. We also investigate the effect of the bias of the cascode transistor of the driver stage on third-order intermodulation distortion and amplitude-to-phase distortion. Consequently, we show that the PMOS driver stage itself acts as a pre-distorter of the power stage. To verify the possibility of the PMOS driver stage and the proposed biasing method for the antiphase technique, we design a 2.42 GHz PA using a 180 nm RFCMOS process for wireless local area network applications. We obtain a measured maximum linear output power of 21.5 dBm with a 23.4% power-added efficiency and an error vector magnitude of 3.14%. We use an 802.11 n modulated signal with 64-quadrature amplitude modulation (QAM) (MCS7) at 65 Mb/s.

A 28 GHz Single-Input Linear Chireix (SILC) Power Amplifier in 130 nm SiGe Technology

This article presents an integrated high-efficiency 28 GHz power amplifier (PA) employing a combination of Chireix outphasing and Doherty architectures in order to simultaneously achieve power back-off efficiency and linearity with a single RF input signal and no predistortion. The amplifier consists of a dual-input high-efficiency outphasing PA and a simple input network which serves as a power splitter and feeds the same signal to the inputs of the main and auxiliary PA cells that are biased in class-AB and class-C regions, respectively, similar to the Doherty architecture. The operation of the PA cells together with the Chireix combiner result in back-off efficiency enhancement plus systematic AM-AM and AM-PM variations which are used to correct the distortions caused by transistors, resulting in a linear response. The implemented PA demonstrates 19 dBm saturation power (Psat) with 34.4% peak power-added efficiency (PAE) and 6 dB back-off PAE of >23% at 27.5 GHz. The modulated signal performance using a 100 MHz 64QAM OFDM signal shows an average output power of 11.9 dBm with PAE >20%, EVM < 5%, and ACLR < −33 dBc without using predistortion.

Millimeter Wave SOI-CMOS Power Amplifier With Enhanced AM-PM Characteristic

This paper proposes a novel inter-stage load-pull characterization method to enhance the linearity of millimeter wave integrated power amplifiers (PAs) by minimizing their amplitude-to-phase (AM-PM) distortion without worsening their AM-AM or efficiency performances. The proposed method identifies the optimal solution for the inter-stage matching network which enables the synthesis of a driver stage AM-PM characteristic that is complementary to that of the power stage; consequently, reducing the overall AM-PM distortion of the PA. The proposed technique is applied to design a proof-of-concept 28–31 GHz PA demonstrator using 45 nm silicon-on-insulator CMOS technology. The measurement results obtained under continuous wave excitation at 29 GHz demonstrate an excellent AM-PM characteristic, with phase distortions as low as 0.2° at the 1-dB compression power level of 13.9 dBm and less than 1° at an output power level of up to 16 dBm (very close to the saturation power of 16.6 dBm). This enhanced AM-PM linearity improves the linearizability of the PA. This was confirmed by testing the PA with a 64 quadrature amplitude modulated test signal with an instantaneous bandwidth of 800 MHz. Without applying any digital pre-distortion (DPD) technique, the PA delivers a power added efficiency (PAE) of 8.7% at an average output power ( $P_{avg}$ ) of 9.4 dBm while maintaining an error vector magnitude (EVM) of −25 dB. However, after applying a very simple memoryless DPD function with only four coefficients, the PA can operate at a higher $P_{avg}$ of 11.1 dBm with a much better PAE of 12.2% while still maintaining an acceptable EVM of −25.2 dB. Thanks to the proposed technique, the PAE of the proposed PA can be improved by 40% with a very simple application of a low cost and low complexity DPD technique.

ESD Protection Design for Open-Drain Power Amplifier in CMOS Technology

The on-chip electrostatic discharge (ESD) protection device for radio-frequency (RF) power amplifier (PA) with open-drain structure is studied in this work. The conventional ESD protection device of stacked diodes and the proposed ESD protection device of stacked diodes with embedded silicon-controlled rectifiers (SCRs) are compared in silicon and applied to the 2.4GHz PAs. The proposed ESD protection device has the advantages including higher ESD-current-handling ability, lower ESD-clamping voltage, and sufficiently low parasitic capacitance. Besides, the proposed ESD protection device does not degrade the PA performances. Therefore, the proposed ESD protection device of stacked diodes with embedded SCRs is more suitable for CMOS PAs.

A 28 GHz 0.18-μm CMOS cascade power amplifier with reverse body bias technique

A 28 GHz power amplifier (PA) using CMOS 0.18 μm Silterra process technology is reported. The cascade configuration has been adopted to obtain high Power Added Efficiency (PAE). To achieve low power consumption, the input stage adopts reverse body bias technique. The simulation results show that the proposed PA consumes 32.03mW and power gain (S21) of 9.51 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 11.10 dBm and maximum PAE of 16.55% with output 1-dB compression point (OP1dB) 8.44 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.

23.5‐30 GHz gallium nitride on silicon power amplifier MMIC with 7.6‐12.4 W saturation output power

AbstractA 23.5‐30 GHz power amplifier (PA) using 0.1‐μm gallium nitride (GaN) on silicon (Si) microwave monolithic integrated circuit (MMIC) process is presented in this work. The area of this PA MMIC is 3.7 mm × 3.2 mm (11.8 mm2). The measured linear gain is 16.4‐19.4 dB with input/output return loss over 10 dB. The measured saturation output power (Psat) is 7.6‐12.4 W under pulsed working condition. The drain voltage is 12 V and the total drain current is 2.6 A, which induce a power added efficiency (PAE) of 26%‐37%. The reported GaN on Si (GaN/Si) PA has high power, high efficiency and low cost. It is more suitable for massive commercial application compared with the traditional GaN on silicon‐carbon (GaN/SiC) PA. As we know, there has been no high output power GaN/Si PA as high as 10 W level reported in the 20‐30 GHz frequency region.

A Multi-Octave Power Amplifier Based on Mixed Continuous Modes

This paper presents a multi-octave power amplifier based on mixed continuous modes. It consists of resistive-reactive series of continuous modes and a phase shift parameter. The issue of impedance duplication is solved in the case of exceeding an octave bandwidth. By introducing a phase shift parameter, the bandwidth is further expanded obviously. Then, a compact network and its design method are proposed to meet impedance requirements. For validation, a 0.5-4.0 GHz power amplifier is designed and fabricated. And the measured results show that the saturated output power is between 40.0 dBm and 42.8 dBm in target band. From 60% to 71% drain efficiency is obtained with a gain greater than 10 dB. The size of the proposed PA is greatly compact, which is only with 3.6 cm $\times6.0$ cm.

An 8–18 GHz power amplifier with novel gain fluctuation compensation technique in 65 nm CMOS * * Project supported partly by the National Natural Science Foundation of China (No. 60123456) and partly by the National 13th Five-Year Project.

A wideband CMOS power amplifier with high gain and excellent gain flatness for X–Ku-band radar phased array is proposed in this paper. Excellent gain flatness is achieved with transformer based matching networks (TMNs), in which the gain fluctuation of an inter-stage matching network can be compensated by the proposed design methods. The circuit is fabricated in the TSMC 65 nm RF CMOS process. The proposed technique is verified by the measurement results, which show that the wideband PA achieves gain of 21–22.5 dB with only ±0.75 dB gain fluctuation and 13–14.6 dBm flat output power between 7.5 and 15.5 GHz, and a little more ripple in the rest of the X–Ku band due to the inaccuracy of passive modelling at high frequency. The circuit delivers saturated and 1 dB-compressed output power of 14.6 and 11.3 dBm respectively at 13 GHz, for a maximal power-added efficiency (PAE) of 23%.

차량 레이더용 77GHz 전력 증폭기 구현

본 논문은 차량 충돌 방지 레이더용 저전력 고이득 77GHz 전력 증폭기를 제안한다. 제안하는 회로는 입력과 단간의 정합을 위한 공액 정합 회로단과 전력이득 증가를 위한 2단 캐스코드 증폭단으로 구성되어 있다. 이러한 회로는 3μm의 최상위 금속 두께 층을 가진 0.18μm Bipolar/CMOS/DMOS(BCD) 1-폴리 4-금속 공정 (fSUBT/SUB/fSUBMAX/SUB= 100/130GHz)을 사용하였다. 이러한 증폭기는 2볼트 전원전압에서 낮은 잡음지수, 낮은 전력소모 및 높은 전력이득을 가지도록 구현되어 있다. 임피던스 정합에 주로 사용하는 넓은 면적을 가진 인덕터 대신 전송선을 이용하여 전체 회로 면적을 줄였다. 제안하는 전력 증폭기는 최근 연구결과와 비교해볼 때 26.8dB의 가장 높은 전력이득, 45mW의 가장 적은 소비전력, 0.152mm²의 가장 작은 칩 면적, 17.5%의 가장 높은 전력부가 효율 특성과 19.5dBm의 가장 높은 포화 출력 전력 특성 보였다.

60-GHz Power Amplifier in 45-nm SOI-CMOS Using Stacked Transformer-Based Parallel Power Combiner

This letter presents the design of a 60-GHz power amplifier (PA) using a new stacked transformer (STF)-based parallel combiner. It begins by highlighting the main limitation of the conventional millimeter-wave (mm-wave) transformer-based parallel combiners, namely, the output parasitic transmission lines. Then, a new STF parallel combiner based on three overlaying coils is proposed. Analyses revealed significant enhancements in terms of self-inductance, quality factors, and coupling factors, which lead to enhanced combining efficiency in the proposed combiner. Subsequently, a two-stage mm-wave PA is implemented in 45-nm silicon-on-insulator CMOS technology. The fabricated PA demonstrates a 3-dB bandwidth equal to 12.5 GHz (50–62.5 GHz). The output power at 1-dB compression/saturation ( ${\mathrm{ OP}}_{\text {1 dB}}/P_{\text {sat}}$ ) and the corresponding power-added efficiencies are recorded as 16.2/18.5 dBm and 18.7/25.5%, respectively.

Design and analysis of four-way power divider for 94 GHz power amplifiers in 90 nm CMOS process

A millimeter-wave miniature CMOS dual-balun-based four-way power divider is reported. The four-way power divider can be applied to a four-way power amplifier (PA) for four-way power dividing or a star mixer for converting the single RF (or LO) input signal to dual differential RF (or LO) signals. In contrast to the traditional four-way PA that uses three two-way Wilkinson power dividers for four-way power dividing, the proposed PA architecture achieves smaller chip area, and higher output power and power-added-efficiency. The four-way power divider occupies a small chip area of 0.16 mm × 0.408 mm (i.e., 0.065 mm2) and achieves S11 smaller than − 10 dB for frequencies of 87.3–101.1 GHz. For frequencies of 94 GHz, the four-way power divider achieves S11 of − 12.2 dB, S21 and S41 of − 8.08 dB, S31 and S51 of − 8.09 dB, and magnitude of amplitude imbalance (MAI) of 0.006 dB and phase difference (PD) of 177° for ports 2–3 and 4–5. For frequencies of 90–100 GHz, the four-way power divider achieves S11 of − 10.5 to − 12.3 dB, S21 and S41 of − 8.09 to − 8.31 dB, S31 and S51 of − 7.9 to − 8.45 dB, and MAI of 0–0.19 dB and PD of 176.8°–178.1° for ports 2–3 and 4–5. The state-of-the-art results of the proposed four-way power divider indicate that it is suitable for 94 GHz image radar sensors.

A 700MHz to 2.5GHz Cascode GaAs Power Amplifier for Multi-Band Pico-Cell Achieving 20dB Gain, 40dBm to 45dBm OIP3 and 66% Peak PAE

Recent development and technology advancement in wireless communication systems to accommodate higher data rate poses a great challenge for wideband operation. This is due to the employment of modulation scheme, such as OFDM, which is subject to high peak to average ratio. Hence communication systems, such as LTE have to operate in multiple operating bands at the moment in order to transmit the OFDM signals linearly with high gain. The power amplifier serves as the bottle neck for high gain linear operation over wide bandwidth. This paper addresses this issue and further presents a novel integrated feedback and analog pre-distortion linearization technique as a solution to achieve wideband flat gain and linear output power while preserving the power amplifier’s power added efficiency (PAE). A maximally flat gain is achieved through the dual parallel feedback technique. The analog pre-distorter on the other hand introduces an optimum third order nonlinear signal components cancellation mechanism over wide frequency range. A prototype of 700 MHz to 2.5 GHz power amplifier is implemented in $0.25~\mu \text{m}$ PHEMT. It achieves an input and output return loss of less than −10 dB followed by flat power gain of 20 dB across the operating band, while sustaining an unconditional stability performance up to 20 GHz. With 1-dB compression point output power (P1dB) of 24.0 dBm, the PA delivers an OIP3 of more than 40 dBm with peak PAE of 66%. The fully integrated circuit consumes an area of 0.8 mm2. The proposed circuit serves to be a good solution to be integrated as a part of the wideband transmitter system for picocell application.

A Dual-Mode Wideband +17.7-dBm 60-GHz Power Amplifier in 65-nm CMOS

This paper presents a 60-GHz power amplifier (PA) utilizing a novel technique to achieve high efficiency at high output power levels. The proposed topology provides the capability of dual-mode operation. The output power of a conventional class-A power amplifier will be combined with the power provided by an amplifier operating at a different class to achieve higher efficiency at higher output levels. An enhanced cascode stage is designed to boost the power gain provided by driver stages coupled to the power stage with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.32-mm2 power amplifier is 17.7 dB at 60 GHz with a wide 3-dB bandwidth of 12 GHz while consuming 378 mW from a 1.2-V supply. A maximum saturated output power of 16.8 dBm is measured with the 14.5% peak power added efficiency (PAE) at 60 GHz. The proposed PA achieved a measured maximum PAE of 17.2% at 18.1-dBm-saturated power operating in high-power mode by applying 1.4-V supply.

High-Efficiency High-Gain 2.4 GHz Class-B Power Amplifiers in 0.13 µm CMOS for Wireless Communications

This paper presents high-efficiency high-gain 2.4 GHz power amplifiers (PAs) for wireless communications. Two class-B PAs are designed and verified in 0.13 µm CMOS mixed-signal/RF process provided by TSMC. The PAs employs cascode topologies with wideband multi-stage matchings. The single-stage cascode PA is designed for a high power added efficiency (PAE) of 35.4% while the gain is 20.4 dB over the -3 dB bandwidth between 2.4 GHz and 2.48 GHz. The two-stage cascode PA is targeted for a high gain of 37.7 dB while it exhibits a peak PAE of 24.1%. Supplied by 1.2 V supply voltages, the PAs consume DC powers of 4.5 mW and 9 mW, respectively.