Efficient 60-GHz Power Amplifier With Adaptive AM-AM and AM-PM Distortions Compensation in 65-nm CMOS Process

Abstract

This article presents a 60-GHz CMOS power amplifier (PA) with an adaptive impedance-compensation linearizer in the 65-nm CMOS process. The proposed linearizer adaptively provides resistance and capacitance that vary appropriately with input power, enabling amplitude-to-amplitude modulation (AM-AM) and amplitude-to-phase modulation (AM-PM) distortions to be compensated simultaneously. The fabricated PA with linearizer on achieves a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB of 12.3 dBm and a peak power-added efficiency (PAE) of 15.6% at such P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB, which demonstrate improvements of 2.8 dB and 6.8%, respectively, compared with the PA with linearizer off. The PA also achieves the peak gain of 31.0 dB, peak saturated power (PSAT) of 15.0 dBm, and peak PAEmax of 22.7%. In addition, the AM-AM distortion at 6-dB output back-off (OBO) is less than 0.1 dB, and the AM-PM distortion at P1 dB is less than 1.5° in the overall 3-dB frequency band. The improvements in both the AM-AM and AM-PM signals lead to a 1.7-dB improvement in OBO at third-order intermodulated distortion of -25 dBc without adding to power consumption.