GHz Low Noise Amplifier Research Articles

Design and Analysis of Low Noise Optimization Amplifier Using Reconfigurable Slotted Patch Antenna

This paper approaches a novel design theory of Low noise amplifier using reconfigurable rectangular shaped slotted patch antenna for 10.3–14 GHz receiver applications. In this approach, a Berkeley short-channel4 metal oxide field effect transistor (BSIM4, MOSFET) device is loaded in rectangular slotted patch antenna which results in wide band frequency of operation. To understand the design and analysis of low noise amplifier, an equivalent circuit model is extracted from the rectangular slotted patch antenna using finite element method (FEM) simulator where the slotted effect is considered. An extraction of equivalent model from the slotted patch antenna results in the L–C circuit which is used to perform an impedance transformation for low noise amplifier. A 12 GHz low noise amplifier using L–C circuit can improve performance parameters as per designer’s requirement. A reconfigurable MOS loaded slotted patch antenna is verified using momentum microwave simulator and a wide bandwidth of 9 GHz in the frequency range of 10.3–19.3 GHz is achieved. The Low noise amplifier is simulated with TSMC 0.09 µm mixed signal/RF CMOS process technology. The post-layout circuit simulation results show that the proposed common source LNA with L–C network achieves a maximum power gain of 20 dB with the −3 dB bandwidth from the range of 10.3–13.6 GHz. A reflection coefficient of −14 dB and minimum noise figure of 1.6 dB is achieved. The power dissipation is 2.5 mW at 1.2 V supply voltage.

Investigation and application of vertical NPN devices for RF ESD protection in BiCMOS technology

BiCMOS technologies have been used to implement the radio-frequency (RF) integrated circuits (ICs) due to the advantages of low noise, low power consumption, high drive, and high speed. The electrostatic discharge (ESD) is one of the important reliability issues of IC. When the ESD events happen, the ESD protection devices must be turned on immediately to protect the ICs, including the RF ICs in BiCMOS technologies. In this work, the vertical NPN (VNPN) devices in 0.18μm silicon-germanium (SiGe) BiCMOS technology with base-emitter shorted and resistor trigger approaches are investigated. In component-level, using transmission-line-pulsing (TLP) and ESD simulator test the IV characteristics and human-body-model (HBM) robustness of the VNPN devices, respectively. In system-level, using ESD gun tests the system-level ESD robustness. The ESD protection of VNPN devices are further applied to a 2.4GHz low-noise amplifier (LNA). After attaching the VNPN devices to LNA, the RF characteristics are not degraded while the ESD robustness can be much improved.

Design and Performance Analysis of 1.8 GHz Low Noise Amplifier for Wireless Receiver Application

In present stereo audio system is a most popular audio system for different purposes. Now a day’s stereo system is commonly used in communication and other purposes. Moreover Normalized Least Mean Square (NLMS) based adaptive filtering is an effective filtering process in case of communication and other applications. However adaptive filtering is an adaptive filter process to cancel out the noise from audio signal successfully. Hence the main objective of this paper is to design a NLMS adaptive filter which cancels out the noise from a noisy wave format stereo audio file. Moreover by varying the order of the adaptive filter (such as 8<sup>th</sup>, 16<sup>th</sup>, 32<sup>th</sup> and 64<sup>th</sup>), the performance of the NMLS adaptive filtered signal with respect to reference and noisy stereo audio signal are analyzed as well.

60 GHz low‐power LNA with high g m × R out transconductor stages in 65 nm CMOS

This Letter presents a 60 GHz low power low noise amplifier (LNA) with high g m × R out transconductor stages in a 65-nm complementary metal oxide semiconductor (CMOS) technology. Different from the cascode and current-reused common source-common source (CS-CS) structure, the new transconductor proposed in this Letter comprises a CS transistor whose DC current is shared by other two transistors. With this configuration, the equivalent transconductance, g m and output resistance, R out of the transconductor are both high while its noise figure is deteriorated slightly comparing with CS structure, making it suitable for low-power LNA circuits. From the measurement results, the LNA gets a gain of 13.4 ± 1.5 dB and 3-dB bandwidth of 16.7 GHz (48-64.7 GHz). The average noise figure of the LNA is 6.1 dB with a power dissipation of 9.6 mW under 1 V power supply.

4–20 GHz low noise amplifier MMIC with on-chip switchable gate biasing circuit

4–20 GHz low noise amplifier MMIC with on-chip switchable gate biasing circuit

5/60 GHz $0.18~\mu m$ CMOS Dual-Mode Dual- Conversion Receiver Using a Tunable Active Filter for 5-GHz Channel Selection

A dual-mode dual-conversion receiver with two far-apart carrier frequencies, 5 and 60 GHz, and two very different channel bandwidths, tens-MHz and GHz, is demonstrated in a standard $0.18~\mu \text {m}$ CMOS technology. The dual conversion architecture receives 60-GHz mode using Schottky diodes at the first conversion stage and merges 5-GHz mode at the second conversion stage. The 5-GHz RF channel selection is achieved by inserting a 20-MHz bandwidth tunable active filter after a 5-GHz low-noise amplifier for the noise concern and before the second down-conversion mixer to relax the linearity requirement of subsequent stages. A tunable active filter with improved linearity using a transformer-coupled scheme is employed. As a result, the narrow 20 MHz channel bandwidth selection at 5-GHz mode shows a 500 MHz tuning range with noise figure of 9 dB and conversion gain of 28 dB. For 60-GHz operation, the 3-dB IF bandwidth is 1 GHz with noise figure of about 20 dB and conversion gain of −3 dB.

An 80 GHz Low-Noise Amplifier Resilient to the TX Spillover in Phase-Modulated Continuous-Wave Radars

An 80 GHz transmitter leakage cancellation circuit is implemented and integrated together with a low-noise amplifier (LNA) as part of a receiver front-end for a phase-modulated continuous-wave radar. The cancellation is achieved by subtracting a copy of the leakage signal from the received one at the output of the LNA. The system incorporates an analog feedback loop to adjust the amplitude of the leakage copy, as well as a vector modulator to adjust its phase. The proposed 80 GHz LNA with transmitter leakage cancellation is implemented in 28 nm CMOS technology and achieves a gain of 15.2 dB, NF of 5.5 dB, and IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of -15.5 dBm while attenuating the transmitter leakage by 27.5 dB.

Design and Simulation of Low Noise Amplifier at 10 GHz By GaN High Electron Mobility Transistor

In this paper, design and simulation of a 10 GHz Low Noise Amplifier (LNA) for Wireless communication systems have been explored. The simulation result has been performed by using the Agilent Advanced Design System (ADS) software. Tuning and optimization tools of ADS software have been used to optimize results. The High Electron Mobility Transistor (HEMT) based on GaN is used for decreasing of Minimum Noise Figure (NFmin) of LNA. Also, for more decreasing NFmin of LNA radial stub elements are implemented in biasing network. We have designed a 10 GHz LNA based on three design manner basing on the lumped, the distributed and radial stub elements. The designed amplifier offers forward gain of 15.72 dB with the noise figure of 1.09 dB at 10 GHz. The input return loss (S11) is equal to -9.635 dB at 10GHz. The output return loss (S22) is equal to -10.009 dB at 10GHz. Also, the isolation (S12) of proposed structure is equal to -22 dB at 10 GHz. The simulation result have shown that the forward gain and noise figure of 10 GHz LNA are optimized noticeably with respect to the pervious works.

Ku-대역 광대역 디지탈 위성방송용 저 잡음하향변환기 개발

본 논문에서는 디지털 위성방송을 수신하기 위하여 Ku-대역 광대역 하향변환기를 설계하였다. 설계된 저 잡음 하향변환기는 잡음 정합에 의한 3단 저 잡음 증폭회로와 10.7~12.75 GHz의 입력신호를 VCO-PLL에 의한 저 위상잡음을 나타내는 4개의 국부발진주파수(9.75, 10, 10.75 및 11.3 GHz)를 형성하고, 디지털 제어에 의하여 4-대역의 IF 주파수 채널을 선택할 수 있도록 설계하였다. 개발한 저 잡음 하향 변환기의 전체 변환이득 64 dB, 저 잡음 증폭기의 잡음지수는 0.7 dB, 출력신호의 P1dB는 15 dBm, band 1 반송주파수 9.75 GHz에서 위상잡음은 -85 dBc@10 kHz를 나타내었다. 설계한 광대역 디지털 위성방송용 하향변환기(LNB)는 국제적으로 이동하는 선박 등의 위성방송용으로 사용가능하다. In this paper, wideband Ku-band downconverter was designed to receiver digital satellite broadcasting. The low-nose downconverter was designed to form four local oscillator frequencies(9.75, 10, 10.75 and 11.3 GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75 GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select intermediate frequency bands by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64 dB, and the noise figure of low-noise amplifier was 0.7 dB, the P1dB of output signal 15 dBm, and the phase noise -85 dBc@10kHz at the band 1 carrier frequency of 9.75 GHz. The low noise block downconverter(LNB) for wideband digital satellite broadcasting designed in this paper can be used for global satellite broadcasting LNB.

글로벌형 다중대역 디지털 위성방송용 Ku-대역 LNB 개발

In this paper, a Multi-Band Ku-band down converter was designed for reception of multi-band digital satellite broadcasting. The Multi-band low-nose down converter was designed to form four local oscillator frequencies (9.75, 10, 10.75 and 11.3GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select an one band of intermediate frequency (IF) channels by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64dB, and the noise figure of low-noise amplifier was 0.7dB, the P1dB of output signal 15dBm, and the phase noise -73dBc@100Hz at the band 1 carrier frequency of 9.75GHz. The low noise block downconverter (LNB) for receiving four-band digital satellite broadcasting designed in this paper can be used for satellite broadcasting of vessels navigating international waters.

Tunable Compact Low-Noise Amplifier With Permalloy Thin-Film Enabled Slow-Wave Transmission Lines

This paper provides a first tunable low-noise amplifier (LNA) design with Permalloy (Py) enabled inductors. Tunable inductor is an important passive device in adaptive radio frequency circuit design. In this paper, a new integrated tunable inductor is implemented utilizing novel slow-wave transmission lines that are built with coplanar waveguide having alternative high and low impedance signal sections, and the Py thin films are deposited and patterned on the signal line of narrow section to provide higher and tunable inductance density. The inductance per unit length has been increased from 877 to 949 nH/m with 100 nm Py thin film at 5 GHz. A tunable 5 GHz LNA utilizing SWLTs is developed, where the tunability of power reflection and power gain of LNA are demonstrated with variable inductors.

A broadband 47–67 GHz LNA with 17.3 dB gain in 65-nm CMOS**Project supported by the National High Technology Research and Development Program of China (No. 2011AA010202).

A broadband 47–67 GHz low noise amplifier (LNA) with 17.3 dB gain in 65-nm CMOS technology is proposed. The features of millimeter wave circuits are illustrated first and design methodologies are discussed. The wideband input matching of the LNA was achieved by source inductive degeneration, which is narrowband in the low-GHz range but wideband at millimeter-wave frequencies due to the existence of gate–drain capacitance, Cgd. In order to minimize the noise figure (NF), the LNA used a common-source (CS) structure rather than cascode in the first stage, and the noise matching principle is explored. The last two stages of the LNA used a cascode structure to increase the power gain. Analysis of the gain boost effect of the gate inductor at the common-gate (CG) transistor is also performed. T-shape matching networks between stages are intended to enlarge the bandwidth. All on-chip inductors and transmission lines are modeled and simulated with a 3-dimensional electromagnetic (EM) simulation tool to guarantee the success of the design. Measurement results show that the LNA achieves a maximum gain of 17.3 dB at 60 GHz, while the 3-dB bandwidth is 20 GHz (47–67 GHz), including the interested band of 59–64 GHz, and the minimum noise figure is 4.9 dB at 62 GHz. The LNA absorbs a current of 19 mA from a 1.2 V supply and the chip occupies an area of 900 × 550 μm2 including pads.

60 GHz CMOS gain‐boosted LNA with transformer feedbacked neutraliser

A 60 GHz low-noise amplifier (LNA) using standard 65 nm CMOS technology is presented. A gain of the 60 GHz amplifier was boosted by using a transformer feedbacked capacitor neutraliser. To stabilise the process variations caused by the positive feedback system, the body node of the triple well was adjusted to tune the capacitor value. The theory, simulation and measurements are presented. An implementation prototype is evaluated using on-wafer proving. The LNA showed a measured peak gain of 30 dB and a measured noise of 4.6 dB under 8.9 mW power consumption with a 1 V supply voltage. The measured IIP3 was −26 dBm. This is believed to be the first CMOS 60 GHz LNA to compensate the overlap capacitor with a single-ended structure.

A 183 GHz Metamorphic HEMT Low-Noise Amplifier With 3.5 dB Noise Figure

This letter presents a 183 GHz low-noise amplifier (LNA), designed primarily for water vapor detection in atmosphere. The LNA requirements were defined by MetOp Second Generation (MetOp-SG) Microwave Sounder, Microwave Imager and Ice Cloud Imager instruments. MetOp-SG is the European contribution to operational meteorological observations from polar orbit. This LNA advances the current state-of-the-art for the InGaAs metamorphic high electron mobility transistor (mHEMT) technology. The five-stage common-source MMIC amplifier utilizes transistors with a gate length of 50 nm. On-wafer measurements show a noise figure of 3.5 dB at the operative frequency, about 1 dB lower than previously reported mHEMT LNAs, and a gain of 24±2 dB over the bandwidth 160-200 GHz. The input and output matching are -11 dB and -10 dB, respectively. Moreover, the dc power dissipation at the optimal bias for noise is as low as 24 mW.

Millimeter-Wave Low-Noise Amplifier Design in 28-nm Low-Power Digital CMOS

This paper presents the design of a 60-GHz low-noise amplifier (LNA) in a 28-nm low-power (LP) bulk CMOS process. As the technology is optimized for digital LP applications, the design of millimeter-wave (mm-wave) circuits requires high-frequency design and modeling of all active and passive devices. This includes the development of a suitable RF-transistor layout, as well as transmission lines and high- $Q$ capacitors. The mm-wave circuit design aspects are further discussed with considerations about possible dc-distribution approaches, broadband matching networks, and optimum transistor loads. The proposed approach and device models have been validated with the fabrication and characterization of a two-stage 60-GHz LNA. This circuit exhibits 13.8 dB of power gain, 18 GHz of bandwidth, 4 dB of minimum noise figure, and an input referred 1-dB compression point at $-$ 12.5 dBm consuming 24 mW of dc power. Based on this performance and to the authors’ best knowledge, the presented amplifier shows the highest reported value for a commonly used figure-of-merit of 60-GHz LNAs.

Design of 5.5 GHz linear low noise amplifier using post distortion technique with body biasing

A highly linear 5.5 GHz low noise amplifier (LNA) has been designed exploiting source inductive degeneration topology by using post distortion linearization techniques in 0.18 m CMOS technology. This technique improves the input third order intercept point $$(IIP_{3})$$(IIP3) of a low noise amplifier. For enhancing the linearity, this technique used a diode connected MOSFET as IMD sinker and forward body biased which is done in cadence tool. The proposed low noise amplifier achieves high $$IIP_{3}$$IIP3 by using two transistors, main and auxiliary transistors. Also source inductive degeneration topology is employed in the proposed LNA to optimize the noise figure (NF) and $$S_{11}$$S11 at high frequency. In order to reduce power consumption and threshold voltage, Forward Body Biased technique was implemented. In this paper, the first section discusses the most widely used eight linearization techniques and in the second section, the proposed circuit is represented along with its employed topology, techniques and the simulated results. The proposed LNA achieves a simulated third order input intercept $$(IIP_{3})$$(IIP3) of 9.20 dBm while consuming 10.8 mW from a power supply of 1.8 V. it also exhibits a measured gain of 11.34 dB and NF, NF of 2.33 dB.

High linearity 24 dB gain wideband inductorless balun low-noise amplifier for IEEE 802.22 band

A 50 MHz---1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network is presented. It was implemented without any inductor and offers a differential output for balun use. Noise canceling and linearity boosting techniques were combined to improve the amplifier performance in such a way that they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 μm × 71 μm area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain >23.7 dB (power gain >19.1 dB), a NF 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 24.7 dB (power gain >19.8 dB), a NF ?0.3 dBm and an S11 <?11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range ?55 to 125 °C was observed for Gain, NF and S11. Power consumption is 18 mW under a 1.2 V supply.

MHEMT $G$-Band Low-Noise Amplifiers

To improve the performance of G-band equipment for humidity sounding of the atmosphere, a high-gain and low-noise amplifier is needed. Here, the performances of 165 and 183 GHz low-noise amplifier microchips intended for atmospheric water vapor profiling application are reported. The microchips are manufactured in metamorphic high-electron mobility transistor technology having a gate length of 50 nm. The on-wafer measured results show noise figures of 4.4-7.4 dB and 16-25 dB gain at the operating frequencies. In addition, two of the amplifiers were assembled in waveguide packages and the measured results show a gain of 19-20 dB and 7 dB noise figure at both 165 and 183 GHz.

Input Balun Embedded Low-Noise Amplifier With a Differential Structure

In this study, we designed a 5 GHz low-noise amplifier (LNA) with a differential structure using 0.18 $\mu{\rm m}$ RFCMOS technology. An input balun is embedded into the LNA to enhance the gain, minimize the noise figure (NF), and miniaturize the overall chip size. The NF is minimized because the loss induced by the passive balun is removed. The first stage of the designed LNA performs the activities of the input balun and serves as the gain stage. To verify the feasibility of the proposed input-balun-embedded amplifier, we designed a typical LNA and the proposed LNA. We obtained a 29.4 dB gain with a NF of 1.85 dB. The measured dc power consumption is approximately 27 mW. The chip size is $1.0\times 0.74 {\rm mm}^{2}$ . From the measured results of the typical and proposed LNAs, we successfully prove the feasibility of the proposed method to minimize the NF and enhance the gain.

243 GHz low-noise amplifier MMICs and modules based on metamorphic HEMT technology

Two compact H-band (220–325 GHz) low-noise millimeter-wave monolithic integrated circuit (MMIC) amplifiers have been developed, based on a grounded coplanar waveguide (GCPW) technology utilizing 50 and 35 nm metamorphic high electron mobility transistors (mHEMTs). For low-loss packaging of the circuits, a set of waveguide-to-microstrip transitions has been realized on 50-μm-thick GaAs substrates demonstrating an insertion loss of &lt;0.5 dB at 243 GHz. By applying the 50 nm gate-length process, a four-stage cascode amplifier module achieved a small-signal gain of 30.6 dB at 243 GHz and more than 28 dB in the bandwidth from 218 to 280 GHz. A second amplifier module, based on the 35-nm mHEMT technology, demonstrated a considerably improved gain of 34.6 dB at 243 GHz and more than 32 dB between 210 and 280 GHz. At the operating frequency, the two broadband low-noise amplifier modules achieved a room temperature noise figure of 5.6 dB (50 nm) and 5.0 dB (35 nm), respectively.