GHz CMOS Power Amplifier Research Articles

CMOS Power Amplifier With Novel Transformer Power Combiner

A novel transformer combiner structure for wattlevel CMOS power amplifier design is presented in this letter. The proposed active skewered transformer (AST) utilizes the slab inductor as the secondary winding and overcomes the quality factor degradation issue when input cells are increased. Slab inductor has been previously used in the distributed active transformer (DAT) as the primary winding and achieved superior passive efficiency for the transformer combined CMOS power amplifier. However, we find that the slab inductor could be more beneficial as the secondary winding when we are aiming for higher output power from the CMOS power amplifier. The full-wave EM simulation has been performed and shows the advantage of AST over the conventional series-combining transformers (SCTs). Finally, a 2.4GHz CMOS power amplifier is designed based on the AST structure and fabricated in 0.18um CMOS process. The measured output power and power-added efficiency of the proposed power amplifier satisfying LTE specification with 5/20MHz bandwidth are recorded as 26.0/25.0dBm and 24.0/20.9%, respectively.

A Fully Integrated High Efficiency 2.4 GHz CMOS Power Amplifier with Mode Switching Scheme for WLAN Applications

A 3.3 V mode-switching RF CMOS power amplifier (PA) for WLAN applications is presented, which is integrated into a 55-nm bulk CMOS process. The proposed PA offers both static control and dynamic power control, allowing it to operate efficiently in both low-power and high-power modes. The pure low-power mode is achieved by reducing power cells, which are also used for linearization in high power mode. The low-power mode is achieved by reducing the number of power cells which are also used for linearization in the high-power mode. In the dynamic power control mode, the total AM–AM and AM–PM distortion is effectively compensated for by dynamically controlling the number of power cells and adjusting the matching input. The proposed PA achieves an output P1dB of 27.6 dBm with a PAE of 32.7% and an output P1dB of 17.7 dBm with a PAE of 10% in high-power and low-power modes, respectively. It is measured with an 802.11 n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 19 dBm under an error-vector-magnitude (EVM) of −27 dB.

A Ka-Band CMOS Power Amplifier With OP1dB Improvement Employing a Diode-Connected Analog Linearizer

This paper presents a 30-36 GHz CMOS power amplifier (PA) with a diode-connected analog linearizer dedicated to improving the output power and power-added efficiency (PAE) at 1-dB output compression point (OP1dB). The proposed analog linearizer performs a gain expansion, simultaneously introducing little phase distortion. In addition, a design procedure of the matching network between the analog linearizer and PA is analyzed to mitigate the impact of impedance variation caused by the control voltage and input power. As a proof of concept, the circuit is fabricated in a 65-nm CMOS process with a 0.31 mm2 total area. Measured output power and PAE at OP1dB are > 13.4 dBm and > 12.4%, where maximum improvement of 2.2 dB and 5.9% is achieved at 31 GHz when the analog linearizer is active. The saturated output power of > 16.2 dBm is obtained with the saturated PAE of > 21%. Applying a single carrier 256-QAM signal with a bandwidth of 400 MHz and a peak-to-average power ratio (PAPR) of 10.4 dB, the PA with the proposed analog linearizer can achieve the adjacent channel power ratio (ACPR) of -34 dBc at the output power of 6 dBm.

Support Vector Machine-Based Model for 2.5-5.2 GHz CMOS Power Amplifier.

A power amplifier (PA) is the core module of the wireless communication system. The change of its specification directly affects the system’s performance and may even lead to system failure. Furthermore, change in the PA specification is closely related to changes in temperature. To study the influence of PA specification change on the system, we used a support vector machine (SVM) to model the temperature characteristics of PA. For SVM modeling, the question of how much experimental data should be used for modeling to meet the requirements is a constant problem. To address this issue, we investigate the effect of different amounts of training data on the modeling of SVM models. The results show that only 75% of the experimental data needs to be used in the modeling process to satisfy the modeling requirements of the SVM model. The number of measurement points required in the PA specification degradation experiment can be reduced by 25%. The results of this paper serve as a guide for planning the number of experimental measurement points and reducing the measurement cost and measurement time.

Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems

A two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage was provided and simulated. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband matching. The shunt peaking topology in a common source configuration is adopted at the second stage to enhance the power gain. The postlayout simulation is performed using the TSMC 65 nm CMOS process operating in a frequency band of 3.1 GHz to 10.6 GHz. The postlayout simulation results indicate that a high flat gain of approximately 22.8 ± 1.2 dB, small group delay variation of ±50 ps, and good input and output matching of less than −10 dB are achieved over the desired working band. Moreover, a saturated output power of 10 dBm and maximum power-added efficiency (PAE) of 29.5% is achieved at 6 GHz. The proposed PA consumes the low power of 15.5 mW from 1.2 V supply voltage.

Design and analysis of a high-performance 90-101 GHz CMOS power amplifier

ABSTRACT A three-stage four–way 90–101 GHz power amplifier (PA) on 90 nm CMOS is reported. The PA consists of a meandrous four-way Wilkinson power divider, and common-source (CS) input and gain stages with inductive shunt-shunt feedback, followed by four-way CS output stage using a compact four-way current combiner. Wideband π-match inter-stage networks are used for broadband impedance and power matching. An LC input network (constituting a series capacitor, a parallel inductor, and an inductive shunt-shunt feedback) is used to convert the input impedance of the input-stage transistors to 50 Ω. This is the way to attain impedance matching at the outputs of the four-way Wilkinson power divider. Besides, an LC output network (constituting a series LC and a parallel inductor) is used to convert the 50 Ω load to the needed series RL load of the four-way current combiner. As a whole, the output-stage transistors operated at the maximal output power (Pout) and power-added efficiency (PAE). At 94 GHz, the PA attains gain of 20.1 dB, saturated Pout (Psat) of 17.5 dBm, and maximal PAE (PAEmax) of 17.7%, one of the best results ever reported for W-band CMOS PAs. The remarkable performance of the CMOS PA reveals its potential for 94 GHz radar systems.

A 5‐11 GHz CMOS power amplifier using Guanella‐type transmission line transformer and adaptive bias circuit

AbstractThis paper presents a 5‐11 GHz fully integrated power amplifier (PA) in tsmc 0.18 μm CMOS technology. The PA utilized broadband and low‐loss Guanella differential transmission‐line transformers (DTLTs) as the input‐ and output‐matching networks to achieve broadband performance. The adaptive bias circuit was adopted to improve the linearity and power added efficiency (PAE) at power back‐off region. The power gain and stability were enhanced by capacitive unilaterialized technique. The PA achieves an output 1‐dB compression point (OP1dB) of 21.75 dBm with 1‐dB bandwidth from 5.5 to 10.5 GHz. The PAEs at peak and P1dB are 21.3% and 23.9%, respectively. The chip dimensions, including all pads, are 1.79 × 1.04 mm2.

A 1.5 ∼ 5 GHz CMOS broadband low-power high-efficiency power amplifier for wireless communications

This paper describes the design of 1.5–5 GHz CMOS power amplifier (PA) for broadband applications that uses 0.18-μm CMOS technology. This UWB PA uses a cascode topology with current-reuse, to enhance the gain at the upper end of the desired band, and a resistive feedback amplifier stage to achieve optimum output power and gain while maintaining a wide bandwidth. The measured results for the proposed UWB PA show an excellent gain in flatness of 20 ± 1 dB over the 2.0–4.0 GHz frequency range. The average gain is about 17.8 dB from 1.5 to 5 GHz. The reverse isolation is less than −42 dBm. The PA has an efficiency of a maximum of 30.5% at 2 GHz, 24.8% at 3 GHz, 28.1% at 4 GHz and 15.2% at 5 GHz with a 50 Ω load termination. The amplifier delivers a P1dB output power of 6.7 dBm and a PAE of 22% at 4 GHz is obtained with a power consumption of 24.5 mW from a 1.8 V supply voltage. The chip area is 1.222 × 1.004 mm2, including the pads. The proposed UWB PA exhibits high gain and is highly efficient. It has the highest FOM for power amplifiers in the 2–6 GHz band.

A 2.4‐GHz CMOS power amplifier using a gain and stability enhancement technique for IEEE 802.11N WLAN applications

ABSTRACTIn this work, we propose a gain and stability enhancement technique with compact size for RF CMOS linear power amplifier applications. The proposed amplifier is designed with differential and cascode structures. To realize a compact size of the power amplifier, the driver stage is merged into the power stage of the power amplifier. To minimize the number of essentially required inductors, the load impedance of the power stage is shared with the driver stage of the power amplifier. Additionally, to moderate stability problems in the power amplifier, the closed loop is removed using a common‐gate transistor, which operates in the saturation region. The power amplifier can then operate in the linear operation. To prove the feasibility of the proposed linear amplifier, we designed a 2.4 GHz CMOS power amplifier using the 180‐nm RF CMOS process. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2265–2268, 2016

Optimal Design of Low Power CMOS Power Amplifier Using Particle Swarm Optimization Technique

A low voltage 2.4 GHz CMOS power amplifier for wireless personal area network (WPAN) applications is presented in TSMC 0.13 $$\upmu $$μm CMOS process. It consists of driver and power amplifier stages which are connected in current reuse structure. The driver amplifier has push pull inverter configuration. The power amplifier is the common source amplifier. These two stages are biased in class AB mode. For optimizing out-of-band emissions, the proposed power amplifier is linearized by RF predistortion technique. For efficient power amplifier, the design parameters are needed to be optimized using particle swarm optimization technique. The optimized power amplifier achieves 0 dBm output power, 34.06 % PAE, 18 dB power gain at 2.4 GHz frequency. It consumes 2.95 mW power at a supply voltage of 1.2 V.

A 60 GHz power amplifier with Psat of 13.1 dBm, PAE of 11 % and excellent matching in 90 nm CMOS for 60 GHz short-range communication systems

A 60 GHz power amplifier (PA) for direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises a cascode input stage with inductive interconnection and load, followed by a common-source gain stage and a common-source output stage with source-degeneration. To increase the saturated output power (PSAT) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss transmission-line inductors are used at the input and output terminals of each of the output stages for wideband input and output impedance matching to 100 Ω. This in turn results in further PSAT and PAE enhancement. The PA consumes 128 mW and achieves power gain (S21) of 11.5 ± 0.4 dB, input-port input reflection coefficient (S11) of ?15.7 to ?17.9 dB, and output-port input reflection coefficient (S22) of ?15.5 to ?30.8 dB for frequencies of 57---64 GHz. In addition, the PA achieves output 1-dB compression point (OP1dB) of 7.5 dBm, PSAT of 13.1 dBm and maximum PAE of 11 % at 60 GHz, one of the best PAE results ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60-GHz short-range communication system applications.

2.4 GHz CMOS power amplifier with mode-locking structure to enhance gain.

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm2.

Design of a 0.7~3.8GHz Wideband Power Amplifier in 0.18-μm CMOS Process

The design of a 0.7~3.8GHz CMOS power amplifier (PA) for multi-band applications in TSMC 0.18-μm CMOS technology is presented. The PA proposed in this paper uses lossy matching network and low Q multistage impedance matching network to improve wideband. To achieve maximum linearity, this PA operates in the Class-A regime. The post-layout simulation results show that the power amplifier achieves 21.9dB of power gain, 22.3dBm of 1dB compression power output at 2GHz. The power adder efficiency (PAE) at gain compression point is 17.8% at 2GHz.

A High‐Voltage Driving 60‐GHz Power Amplifier with Psat of 13 dBm and PAE of 9.1% in 90‐nm CMOS for IEEE 802.11ad Communication Systems

ABSTRACTA high‐voltage (3 V) driving 60‐GHz power amplifier (PA) for direct‐conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises two cascode stages with inductive load and low‐impedance interstage matching, followed by a common‐source output stage. To increase the saturated output power (Psat) and power‐added efficiency (PAE), the output stage adopts a two‐way power dividing and combining architecture. Instead of the area‐consumed Wilkinson power divider and combiner, miniature low‐loss LC power divider and combiner (IL = 0.536 dB @60 GHz) are used. This in turn results in further Psat and PAE enhancement. The PA consumes 176.2 mW and achieves power gain (S21) of 17.9 ± 3.7 dB, input‐port input reflection coefficient (S11) of −5.8 to −7.3 dB, output‐port input reflection coefficient (S22) of −10.4 to −26.3 dB, and reverse isolation (S12) of −56.4 to −81.7 dB for frequencies 50–60 GHz. In addition, for frequencies 50–60 GHz, the PA achieves output 1‐dB compression point (OP1dB) of 6.6–7.8 dBm, Psat of 10.6–13 dBm and maximum PAE of 9.1%, one of the best PAE results ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60‐GHz short‐range communication system applications. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2033–2039, 2013

A high-performance CMOS power amplifier for 60 GHz short-range communication systems

A 60 GHz power amplifier for direct-conversion transceiver using standard 90 nm CMOS technology is reported.The power amplifier comprises three cascaded common-source stages with inductive load and inter-stage matching. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss LC power divider and combiner are used. This in turn results in further Psat and PAE enhancement. Over the 57 ∼ 64 GHz frequency band of interest, the power amplifier consumes 44.4 mW and achieves power gain (S21) of 12.04 ± 1 dB, input-port input return loss (S11) of −6 to −9.4 dB, output-port input return loss (S22) of −10.4 to −26.4 dB, and reverse isolation (S12) of −29.2 to −30.6 dB. At 60 GHz, the power amplifier achieves Psat of 11.4 mW and maximum PAE of 15.8%. To the authors' knowledge, this is the best PAE ever reported for a 60 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP1 dB) is 6 dBm at 60 GHz. These results demonstrate that the proposed power amplifier architecture is very promising for 60-GHz short-range communication systems. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1155–1160, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27522

60 GHz CMOS power amplifier with P sat of 11.4 dBm and PAE of 15.8%

A 60 GHz power amplifier (PA) for a direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises three cascaded common-source stages with inductive load and inter-stage matching. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, a miniature low-loss LC power divider and a combiner are used. This in turn results in further Psat and PAE enhancement. Over the 57–64 GHz band of interest, the PA consumes 44.4 mW and achieves a power gain (S21) of 12.04±1 dB. At 60 GHz, the PA achieves Psat of 11.4 mW and a maximum PAE of 15.8%. To the authors’ knowledge, this is the best PAE ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60 GHz short-range communication systems.

5–11 GHz CMOS PA with 158.9 ± 41 ps group delay and low power using current-reused technique

This paper proposes the design of a low group delay and low power ultra-wideband (UWB) power amplifier (PA) in 0.18μm CMOS technology. The PA design employs two stages cascade with inductive peaking technique to provide broad bandwidth characteristic and higher gain while gain flatness can be achieved by connecting inter-stage circuit. A common gate current-reused technique is adopted at the first stage amplifier to achieve good input matching, low group delay and low power. The simulation results show that the proposed PA design has an average gain of 11.5dB with flatness of ±0.4dB from 5–11GHz, while maintaining bandwidth of 4.2–12.3GHz. An input return loss (S11) less than −10.4dB and output return loss (S22) less than −9.5dB, respectively are obtained. The PA design achieves excellent phase linearity (i.e., group delay variation) of ±41ps and only consuming 17mW power from 1.2V supply voltage. A good output 1-dB compression point OP1dB of 3.7dBm is obtained. By using this method, the proposed design has low group delay variation and lowest power among the recently reported UWB CMOS PAs applications.

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner

A 1V, 69–73GHz CMOS power amplifier based on improved Wilkinson power combiner is presented. Compared with the traditional one, the proposed Wilkinson power combiner could lower down the insertion loss and reduce the die area by eliminating the quarter-wavelength transmission lines while preserving the characteristics of Wilkinson power combining and good port isolation. The presented power amplifier has been implemented in 65nm CMOS process and achieves a measured saturated output power of 10.61dBm and a peak power added efficiency of 8.13% at 73GHz with only 1V power supply. The die area including pads is 1.23×0.45mm2, while the power combiner only occupies 200×80μm2.

A 60 GHz CMOS Power Amplifier With Built-in Pre-Distortion Linearizer

A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 10.72 dBm and OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB of 7.3 dBm from 1.2 V supply. After linearization, the OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

A 14.3% PAE parallel class-A and AB 60GHz CMOS PA

At 60GHz, it becomes difficult to achieve a high power added efficiency (PAE) and large output power for CMOS power amplifier (PA). A parallel class-A and AB pseudo Doherty PA is designed in CMOS 65nm process to obtain a high PAE and large output power. The PA achieves a 9.8-dB gain at 60GHz. The measured large signal results show that a maximum power added efficiency (PAE) of 14.3% and 12.0% at 1dB compression point are realized. The chip consumes 45∼58mW power from a 1.2-V supply voltage. The chip area is 0.6mm2 including pads.