GHz CMOS Power Amplifier Research Articles

An Excellent Gain Flatness 3.0–7.0 GHz CMOS PA for UWB Applications

This letter presents an excellent gain flatness CMOS power amplifier (PA) for UWB applications at 3.0-7.0 GHz in TSMC 0.18 μm CMOS technology. The UWB PA proposed here employs a current-reused technique to enhance the gain at the upper end of the desired band, a shunt and a series peaking inductors with a resistive feedback at the second stage to obtain the wider and flat gain, while shunt-shunt feedback helps to enhance the bandwidth and improve the output wideband matching. The measurement results indicated that the input return loss ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) less than -6 dB, output return loss ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">22</sub> ) less than -7 dB, and excellent gain flatness approximately 14.5 ±0.5 dB over the frequency range of interest. The output 1 dB compression of 7 dBm, the output third-order intercept point (OIP3) of 18 dBm, and a phase linearity property (group delay) of ±178.5 ps across the whole band were obtained with a power consumption of 24 mW.

High efficiency, good linearity, and excellent phase linearity of 3.1-4.8 GHz CMOS UWB PA with a current-reused technique

This paper describes the design of 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using 0.18-μm CMOS technology. The UWB PA proposed here employs cascode topology with a current-reused technique to enhance the gain at the upper end of the desired band, an inter-stage inductor, and a resistive feedback at the second stage to obtain the flatness gain. The measurement results indicated that the input return loss (S11) was less than -5 dB, output return loss (S22) was less than -8 dB, and average power gain of 10.3 dB with a flatness about 0.8 dB. The input 1 dB compression point about -2 dBm and excellent phase linearity (group delay) of ±135 ps across the whole band were obtained. Moreover, a very high power added efficiency (PAE) of 40.5% at 4 GHz with 50 Ω load impedance was achieved with a power consumption of 24-mW.

A 2.3GHz linearized CMOS power amplifier with AM-AM and AM-PM distortion correction

A linearized 2.3GHz CMOS power amplifier with AM-AM and AM-PM distortion correction is presented. The varactors are used at the driver amplifier load to correct the phase distortion and gate bias control of the PA to compensate the amplitude distortion. The proposed CMOS PA has been implemented in 0.13µm CMOS technology. The measured results show that P1dB is increased 1.6dB and PAE is improved from 5.5% to 9% at the condition of -28dB EVM, respectively.

A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 mum CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 802.16e signals.

A CMOS RF predistorter using diode‐connected MOSFET

AbstractIn this paper, a RF predistorter designed using a CMOS process is reported. In GaAs circuits, a Schottky diode has been used as a nonlinear element in the hybrid type predistorter linearizer. We propose a diode‐connected MOS transistor as an alternative nonlinear element in CMOS process. For the analysis, the idea of a dynamic impedance line is introduced and the large signal equivalent parameters of the nonlinearity generation circuit are extracted from the simulation. A 2.4 GHz CMOS power amplifier is designed using a 0.18‐μm CMOS 1P6M mixed‐mode process and the proposed predistorter is fully integrated with the CMOS power amplifier in a single chip. The measured results match with the simulation results. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2055–2057, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22646