A 1.5 ∼ 5 GHz CMOS broadband low-power high-efficiency power amplifier for wireless communications

Abstract

This paper describes the design of 1.5–5 GHz CMOS power amplifier (PA) for broadband applications that uses 0.18-μm CMOS technology. This UWB PA uses a cascode topology with current-reuse, to enhance the gain at the upper end of the desired band, and a resistive feedback amplifier stage to achieve optimum output power and gain while maintaining a wide bandwidth. The measured results for the proposed UWB PA show an excellent gain in flatness of 20 ± 1 dB over the 2.0–4.0 GHz frequency range. The average gain is about 17.8 dB from 1.5 to 5 GHz. The reverse isolation is less than −42 dBm. The PA has an efficiency of a maximum of 30.5% at 2 GHz, 24.8% at 3 GHz, 28.1% at 4 GHz and 15.2% at 5 GHz with a 50 Ω load termination. The amplifier delivers a P1dB output power of 6.7 dBm and a PAE of 22% at 4 GHz is obtained with a power consumption of 24.5 mW from a 1.8 V supply voltage. The chip area is 1.222 × 1.004 mm2, including the pads. The proposed UWB PA exhibits high gain and is highly efficient. It has the highest FOM for power amplifiers in the 2–6 GHz band.